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Plasma globe works but ran into a problem

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boylesg

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I have built a plasma globe driver based on this circuit: http://www.stevehv.4hv.org/FBD/FBschematic.JPG

I powered the FET part of the circuit with 80V and the 555 part of the circuit with 16V

And here are the results: https://www.gregsindigenouslandscapes.com.au/movies/PlasmaGlobe.mp4

However I tried powering the FET part of the circuit with 100V DC and I smoked 2 TC4433 chips (8 pin pdip rather than TO-220)

Now I could try and test what is going on with my oscilloscope but it would mean smoking more of the chips. And it happens quite quickly so I would not have enough time to view any voltage spikes going into the TC4422 anyway.

Can anyone give me some tips as to what is likely to be causing the TC4422 to smoke?

Perhaps a kick back issue from the 100V side of the gate drive transformer sending a voltage spike into the output of the TC4422 that is exceeding the voltage rating of the output transistors inside it?

I could try the TO-220 package, but I am unsure whether I am likely to have the exact same issue with it smoking as well due to any voltage spikes.

Perhaps I should put a diode based snubber on the output of my TO-220?
 

betwixt

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Possibly the transformer is overloading the TC4422 (not TC4433 I assume). Try adding a 1 Ohm resistor in series with it's output pin to limit the current a little. If that doesn't work, try voltage protection at it's output by fitting a fast diode from output to ground and output to +12V, both wired 'non conducting' so only reverse or over voltage makes the diodes conduct.

Brian.
 

boylesg

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I have been fiddling around with this: Calculator.jpg

Rather than a kick back problem, I think I still have a power dissipation problem, and I may have just been lucky that the TC4422 didn't smoke earlier before I started powering the FET from 100V DC.

The total power dissipation for the pdip package is about 750mW and according to my calculations in the spread sheet above I am way in excess of that even having used 180nF for C5 (between the TC4422 output and GDT primary) rather than 680nF.

It all depends on how the author implemented his GDT and what the inductance of his GDT primary was.

I used the core from a tv flyback transformer and 15 turns for the primary which gives me an inductance of 160uH.

It looks as though I will have to go to an even lower value again for C5 to increase the total reluctance in order to bring down the current draw on the TC4422 to a more acceptable level....even if I switch to the TO-220 package.

I used 16V as the supply to TC4422 which will be making the current draw from it greater than the author's circuit.

Oh and the duty cycle of roughly 70% probably will be reducing the total power output of the TC4422 that my spread sheet is calculating, but at least it give me an idea of where I am at with power dissipation.

I can heat sink the TO-220 package and increase the power dissipation from 1.6W to 16W or so and that will add another layer of protection in addition to your diode idea.

Perhaps the still high current draw on my TC4422s plus a kick back from the 100V DC FET supply tips the TC4422 over the edge.

- - - Updated - - -

Possibly the transformer is overloading the TC4422 (not TC4433 I assume). Try adding a 1 Ohm resistor in series with it's output pin to limit the current a little. If that doesn't work, try voltage protection at it's output by fitting a fast diode from output to ground and output to +12V, both wired 'non conducting' so only reverse or over voltage makes the diodes conduct.

Brian.
Rectifier diodes or 16V zener diodes do you think?


The datasheet for TC4422A does not have the power dissipation of the packages at the top like the datasheet for TC4422 does. Bloody pain!

You wouldn't happen to have a copy of the TC4422A datasheet with this missing info would you Brian?

- - - Updated - - -

With a heat sinked TO-220 TC4422 it looks as though I could go a 220nF cap for C5.

That give me a power dissipation of around 12W according to my spreadsheet......times 0.7 because my duty cycle is around 70% probably.

So that should bring the power dissipation below 12.5W (heat sinked) as specified in the TC4422 datasheet.

Plus the fact that the newer TC4422As have a higher output current rating and therefore presumably a higher allowable power dissipation.
 
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SunnySkyguy

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The TC4421A/TC4422A are improved versions of the earlier TC4421/TC4422 family of single-output
MOSFET drivers. https://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en023175

The result is better dead time and separate hi/lo outputs to control dead time in next stage.

The problem is not that RdsOn is 2 Ohms max but that the Crossover Energy exceeds rated max of ~ 100 [A-ns] per cycle or 50 A-ns per half cycle.

Add R increases ns time constant but reduces A and input A from I=dv/dt*CISS of the FETs increases with delta Vds and insufficient cross conduction dead time.

Thermal Resistance, Rja =155 °C/W 8L-SOIC will be a limiting factor also assuming proper PCB design implementation of the insulated Exposed Pad (EP)

I suggest you measure your dead-time with a variable current limited power supply or do the math on prop delay for each polarity edge.
 

boylesg

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The TC4421A/TC4422A are improved versions of the earlier TC4421/TC4422 family of single-output
MOSFET drivers. https://www.microchip.com/mymicrochip/filehandler.aspx?ddocname=en023175

The result is better dead time and separate hi/lo outputs to control dead time in next stage.

The problem is not that RdsOn is 2 Ohms max but that the Crossover Energy exceeds rated max of ~ 100 [A-ns] per cycle or 50 A-ns per half cycle.

Add R increases ns time constant but reduces A and input A from I=dv/dt*CISS of the FETs increases with delta Vds and insufficient cross conduction dead time.

Thermal Resistance, Rja =155 °C/W 8L-SOIC will be a limiting factor also assuming proper PCB design implementation of the insulated Exposed Pad (EP)

I suggest you measure your dead-time with a variable current limited power supply or do the math on prop delay for each polarity edge.

I am an amateur here so I am little confused by the technical language you have used, but it sounds to me that you are effectively saying that the impedance in my TC4422 output circuit is to low resulting in to many high amp pulses too close together with the pdip version of the TC4422 being unable to dissipate the resulting heat fast enough.

Is this essentially correct Tony?

If so I sort of came to the same conclusion from my Excel spread sheet capacitive/inductive impedance calculator I was fiddling around with.

But there is something else going on as well.

My pdip TC4422A was fine (or seemed to be) for the short time periods I was running the plasma globe) when the FETs were powered with 80V.

But as soon as I connected the FETs up to 100V DC, the pdip TC4422 when up in a puff of smoke almost immediately. So there must be some additional factor that is tipping the pdip TC4422s over the edge of their limits.

My amateur assessment was that it was a higher kick back voltage spike, due to the 100V rather than 80V, propagating back through the gate drive transformer and into its primary winding, combined with the probably too low impedance in TC4422A output gate drive transformer circuit. Such that there is insufficient recovery time for the TC4422 that you appear to have pointed out above.
 

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