sanjaysharmaiitk
Member level 1
syntheses of a 8 bit counter has been completed through design compiler( synopsys cad tool ) after that gate-level-netlist file generated from design compiler and two LEF library file file are used for beck-eng design through innovus cad tool.
there are problem in placement of standard cell during placement tool skip the all buffer buff cell those are used in gete-level-netlist so problem came in lvs match.
how to place buffers along with standard cell. i got nothing despite applying many method.
i have uploaded gate-level-netlist of 8bit counter
in above gate-level-netlist
cell U4 ,U5 ,U15, U16 are buffd1 cell.
before placement buffd1 cell are seeing on innovus window
but a after placement buff cell are skipped by tool.
i also checked LEFF library file that have definition of buff.
how to place buffers along with standard cell.
there are problem in placement of standard cell during placement tool skip the all buffer buff cell those are used in gete-level-netlist so problem came in lvs match.
how to place buffers along with standard cell. i got nothing despite applying many method.
i have uploaded gate-level-netlist of 8bit counter
in above gate-level-netlist
cell U4 ,U5 ,U15, U16 are buffd1 cell.
before placement buffd1 cell are seeing on innovus window
but a after placement buff cell are skipped by tool.
i also checked LEFF library file that have definition of buff.
how to place buffers along with standard cell.