Place and route on flat full chip

[jaya sree]

Hi all ,

I am doing place and route on flat full chip for the first time.Please provide any material on this . Previously I have worked on partitioned blocks.But with full chip , there many new things to consider ( PADS etc.). I would like to know what must be done/not done at chip level.It would be helpful if any study documents is provided.

Thank you

 

[lohi21]

All entities of PD remains the same for the block level and chip level, except that you you will floorplan the design considering the package, (Wirebond or flip chip). Power planning, this time you will have to come up with the total power consumption by the chip and plan accordingly. just run the complete flow and take it to sign off tools and see what violation u can see, and do floorplan accordingly.

Many more, But each chip is indegineous to itself. Try to ask in specific. May the Eda board members can answers as and then.