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Place and Route - LVS Short net Error

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Shady Ahmed

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I designed a 5 stage pipelined RISC processor in VHDL, synthesized the code using ARM libraries on 65nm Technology using synopsis Design Vision Tool.
Also, post synthesis simulation is correct.

At the place and route stage, i am using IC Compiler (Synopsys)..
However , no matter what i do, i get Zero DRC errors, however 2 LVS errors ( 2 Shorted Nets : VDD & VSS)..

I tried various parameters, i tried utilization factor 0.4 -> 0.7
I also tried different number of power straps ..

* VDD & VSS Horizontal Straps.
* VDD & VSS Vertical Straps.
* VDD & VSS BOTH Vertical and Horizontal Straps.
* VDD Horizontal straps & VSS on vertical Straps.

With all these different combinations, i always get the LVS errors mentioned before, what is the problem ? and what should i do ?
 

jbeniston

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Sounds like some of your VDD and VSS nets are shorted together. Does the LVS tool not give you a marker where the short is?

If not, perhaps you can trying running LVS after each step in your script to see which command introduces the short.
 
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