Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

pipeline ADC- parasitic input capacitance HELP!

Status
Not open for further replies.

ljy4468

Full Member level 4
Joined
Jul 20, 2005
Messages
232
Helped
13
Reputation
26
Reaction score
1
Trophy points
1,298
Location
South Korea
Activity points
3,023
hi all
I've a question about amp parasitic input capacitance.
In pipelined ADC 1.5bit stage, in the MDAC amplification mode,
feedback factor is 0.5.(neglect input parasitic capacitance).

but without neglecting opamp's parasitic capacitance, feedback factor is
much smaller.

Now, I've a question about that.
For calculate input parasitic capacitance,
for NMOS input driver, cap is about L*W*(mos capacitance per um2)
that's ok
but PMOS input driver, Same calculation?????
Pmos's body is vdd.So very confused.
Somebody helps me!!!!
 

gigle

Junior Member level 1
Joined
Feb 9, 2006
Messages
19
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,479
The same....

But for both nmos and pmos device the Cgs in saturation region is (2/3)WLCox, not just WLCox.

And you have to take (1+beta)Cgd into account. Usually you can not ignore this component. beta is the gain from gate to drain of input device.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top