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protonixs said:i dont have any docs to share but i could give some tips.
first plan for the power routing coz it is very difficult to lay it out if it is not well planned. you may consider using the grid technique to save space; but of course u need a process that uses at least 5metals. different power lines are used in this topology; one for the digital part (clock), one for the comparator (flash ADC and DAC), and one for the analog part (diff amps). they must be separated from each other coz one introduces different noise while others should be kept away from those noise. Proper shielding should be employed to isolate noisy blocks from others.
One important point in designing pipeline ADC is the matching. This is the top priority in order for the layout to function. Unwanted delays (parasitic RC) should be avoided.
You must put matched device as near as possible to avoid mismatches. Dont worry about the dead space that would be created as you go on designing coz they will be filled up with bypass capacitors. Dont put the clock devices far from the one it controls because it may cause unwanted delays; but dont put it too near that it introduces noise to the analog parts.
should you have more question or clarification, dont hesitate to ask again.
hope this helps.
tnx and regards,
shineqi said:Would you mind sharing some experices dealing with that?