Sep 1, 2018 #1 P Puppet123 Full Member level 6 Joined Apr 26, 2017 Messages 356 Helped 22 Reputation 44 Reaction score 21 Trophy points 18 Activity points 3,059 Hello, I want to design Pipeline ADC in 65nm CMOS. At this low voltage, what considerations should I use for the opamp ? Would I have to use gain boosting to get the gain I need for say 10 bit operation ? If anyone can provide guidance, or resources, please do. Thank you.
Hello, I want to design Pipeline ADC in 65nm CMOS. At this low voltage, what considerations should I use for the opamp ? Would I have to use gain boosting to get the gain I need for say 10 bit operation ? If anyone can provide guidance, or resources, please do. Thank you.
Sep 1, 2018 #2 erikl Super Moderator Staff member Joined Sep 9, 2008 Messages 8,108 Helped 2,695 Reputation 5,370 Reaction score 2,305 Trophy points 1,393 Location Germany Activity points 44,123 Here's an IEEE paper on this subject.