Pin to Clock routing warning after implementation

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msdarvishi

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Dear all,

I am using Vivado2017 targeting a Zedboard including a Zynq-7000 (clg484) FPGA.

I am trying to transmit a signal as a clock between two FPGA Zedboards via FMC connectors. At the Destination board, I take the signal from an N-pin of FMC, and the synthesizer with apply an IBUF for that. Then I instantiated a BUFG in order to consider that signal as a clock to be fed to the flip-flops of my design. The design completely synthesized with no warning or error and also the implementation succeed with no errors, but I receive the following warning in implementation.

Can anyone help me to pass this issue?




Kind replies are in advance appreciated.

Regards,
 

Hi,

The message describes the problem and also gives a hint to get around.

You have 2 options.
1> Downgrade the error to a warning by use of the CLOCK_DEDICATED_ROUTE constraint is set to FALSE in your xdc.
2> Choose another IO pin to feed in your clock.

It has also been repeatedly answered in the Xilinx forums. Please read the thread below and other related threads.
http://forums.xilinx.com/t5/Virtex-...DICATED-ROUTE-FALSE-in-some-cases/td-p/697472
 

is this an issue with the pin being poorly located -- eg, the clock pin not having dedicated routing to the global clock network -- or just using the wrong component? You might be able to use an IBUFG instead of the IBUF. The IBUFG/IBUFGDS are used to connect an input buffer that can be connected to a BUFG to a BUFG.
 



Hello,

Thanks for your reply. Once I put an IBUFG and a BUFG in my VHDL, after synthesis, the IBUFG is changed to an IBUF and in implementation process, I get the following ERROR since there are an IBUF (not an IBUFG) and a BUFG in series:



but if I only use an IBUFG in my VHDL file, the synthesizer will change it to an IBUF, but after implementation finished completely, the following Warning appears rather than the Error message that I have mentioned above:




An issue here: Does this warning message will hurt the design??

I am confused between two choices:

(1) If I put an IBUFG and then a BUFG in my HDL file, the synthesizer will change IBUFG to an IBUF and gives the Error message shown in my previous post;

(2) If I put only an IBUFG in my HDL file, the synthesizer will change IBUFG to an IBUF and gives the Warning message shown above

I do not know how to pass this issue?!
Thanks and Regards,
 

What specific package and pin for the Zynq part does this FMC connector pin go to. If it does not go to a clock capable pin you will receive the message you have been getting.

The only way to fix this would be to pick another FMC connector pin that does go to a clock capable input pin on the Zynq. Or alternatively ignore the warning, if you don't care about using an uncompensated clock. The timing path of the IBUFG-BUFG combination is known by the tools and it uses this information when it compensates for the clock input delay when using MMCMs. If you are using the clock directly you won't have that issue, but the pin to BUFG delay will possibly vary much more widely over PVT and you will need to account for that if it matters to external devices (setup/hold).
 

ads-ee said:
What specific package and pin for the Zynq part does this FMC connector pin go to. If it does not go to a clock capable pin you will receive the message you've been getting.
Click to expand...

Dear ads-ee,

I am using Zynq-7000 (XC7Z020CLG484-3) and all the "N-pins" of FMC connector go to the individual clock pins of D flip-flops. The flip-flops.

Do you mean that this warning message is normal and can be ignored without any interference and problem?

Thanks,
 

That doesn't tell me which FMC pin goes to which pin of the Zynq part.
 

ads-ee said:
That doesn't tell me which FMC pin goes to which pin of the Zynq part.
Click to expand...

I configured the connections in FMC pins on the Zynq board by using the following constranits in my XDC file:



I use ONLY the N pins, totally 34.
 

You have to use one of the following pins circled in red the ones with MRCC or SRCC for multi-region and single-region respectively. Most likely you will want to use one of the MRCC pins.

- - - Updated - - -

Oops here is the picture
 

ads-ee said:
You have to use one of the following pins circled in red the ones with MRCC or SRCC for multi-region and single-region respectively. Most likely you will want to use one of the MRCC pins.
Click to expand...

Sorry I did not get what you mean! What are MRCC and SRCC and how to identify them??

- - - Updated - - -


I need and have to use ALL N-pins of FMC which are totally 34. The red circule that you mentioned does not cover all N pins. How can I use all of them then?? Also, the schematic that I have for the Zynq FPGA used, does not have MRCC or SRCC pins...!
 

msdarvishi said:
I configured the connections in FMC pins on the Zynq board by using the following constranits in my XDC file:

I use ONLY the N pins, totally 34.
Click to expand...

Why are you using only the _N pins? For regular single ended signals you can use both _N and _P pins. For clocks thought they they typically should be on the _P pin as it is the "master" IO cell of a differential pair as it is the one with the direct connection to the BUFG. Using the _N pin as a single ended clock is the same as using any other generic pin and will generate the warnings you are seeing.
 


Thank you for pointing out the nice comment for the difference between N and P pins of FMC. Indeed, ALL other P pins of FMC will be used by my colleague and I will use ALL of N pins. So, I have no ways except do this strategy. As you said, the warning is due to this reason that I am using ONLY N pins of FMC as a single ended clock to some flip-flops. Is it any way to solve these warnings based on your explanation??
 

msdarvishi said:
Sorry I did not get what you mean! What are MRCC and SRCC and how to identify them??
Click to expand...
They are part of the I/O names used by Xilinx for the Zynq.
They are also described in the following from the clocking resource users guide.


msdarvishi said:
I need and have to use ALL N-pins of FMC which are totally 34. The red circule that you mentioned does not cover all N pins. How can I use all of them then?? Also, the schematic that I have for the Zynq FPGA used, does not have MRCC or SRCC pins...!
Click to expand...
I was only circling the clock capable pins from a Zedboard schematic. If the schematic you have doesn't have what is on that schematic then you don't have a "real" Zedboard. I still don't get why you want to use only "slave" I/O of a differential pair...
 


Surprisingly, the IBUFG instantiation in VHDL is translated as IBUFG in Xilinx ISE 14.7 while it is translated to IBUF in Vivado 2017.1 ...!!!! It seems weird and I do not yet know why...
 


IMO this is a really idiotic way of deciding who gets what pins.

Just cut the bus in half based on the bank...you get the top half they get the bottom half. You each get a clock pin and the upper or lower half of the FMC pins.
 

ads-ee said:
IMO this is a really idiotic way of deciding who gets what pins.

Just cut the bus in half based on the bank...you get the top half they get the bottom half. You each get a clock pin and the upper or lower half of the FMC pins.
Click to expand...


If this way is idiotic, then if we cut the FMC bus in half, so the number of pins than I can use will be less than 34 since each N-P pair of FMC connectors must carry different signals (P pin is signal0 and pin N is signal1) and these signals are not invert of each other. Doesn`t it matter, then??
 


What, that makes absolutely no sense whatsoever!? The P and N only stand for differential signals, if you use them as all single ended, which must be what you are doing it won't matter. The P and N don't specify inverted signals unless you are using them as a differential standard, which you obviously can't be doing as you and your colleague are using half of the pair to begin with. Who came up with this silly way of dividing the pins up?

The biggest problem with using those differential pairs is they are likely run as 100 ohm differential pairs and will therefore have cross talk issues. At least if you control both P and N pairs you can perhaps be more selective about the signals that are next to each other.
 


Thank you very much @ads-ee for this clarification. Ok, I will devide the FMC pins in half based on the banks. But I do not know how to initiate the following clock pins of FMC in my XDC file where I have ONLY 1 clock signal that is sys_clk. Can you give me a hint on that what to do with that?




If I use my sys_clk signal as FMC_CLK1_P, then what should I do with FMC_CLK1_N?
Thank you,
 

Use it as any other pin, it doesn't have to be a clock, but it's much more likely to have cross talk issues as it has an actual clock paired with it.
 

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