Pin count exceeded in RC4 Analysis

[shikharmakkar]

I am working on the hardware implementation of RC4 cipher and has written the code for it using ASM design methodology and the key and plain text are given by the user through two input ports of integers. After running Analysis and Synthesis, the device uses around 800 pins and Altera Quartus II Web Edition supports FPGA having max pins of around 520. What should I do? I tried using pin assignment but didn't understand it. While I run the compilation, it shows that only a few pins, around 300 drive logic. How can I remove the useless pins? I need to do this because I have to compare RC4 basic version with its other versions like RC4+.

 

[FvM]

How about shifting-in key and data serially?

I presume, you are not designing real hardware rather than testing synthesis of your RC4 design. Because no clearheaded hardware dessigner would connect several hundred signals through individual pins.

 

[shikharmakkar]

Can you please explain key shifting? Yes, I am testing the hardware implementation for my university project and not synthesizing it on FPGA but for timing analysis, I need to reduce the pin count to around 500.

 

[std_match]

Try using "virtual pins":

https://electronics.stackexchange.com/questions/92185/setting-fpga-pins-as-virtual
https://chandujjwal.blogspot.de/2011/05/declaring-virtual-pins-in-quartus.html

 

[ads-ee]

It might be worth taking virtual pins a step further and add the sources and probes megafunction to the design, then the OP can directly control the values on those "virtual pins" without having to figure out how to drive some external interface.