PIC 18 Architecture studying

[PA3040]

Dear All
Please find the attached picture

It would be much appreciated if some one can explain the each block of PIC

Thanks in advance

 

[wp100]

Hi,

Do not think you will find anyone giving you such a detailed breakdown of the memory.

You will find all the details of the Pic18F memory in the datasheets eg pic18F4520 datasheet.

It may seem a difficult read but it does come together eventually.

It is important you be aware of all those numbers in that picture which show the bit width of each bus, example the program memory address bus is 21 bits but the data ram address bus is only 12 bits.

What you can also do, is use MPlab SIM and code some simple data moves and then View the addresses and data in the File Registers, Hardware Stack and Watch Windows etc, so you can see your learning in practical views.

 

[PA3040]

Hi wp100,
Thanks for the valuable information

Can you please see my new updated picture and it would much appreciated if you can say some thing about red being

Thanks in advance

 

[wp100]

Hi,

If you are asking what does that flow icon mean, then it would seem to be the logic needed to accept the address from those two sources.

What I cannot see is, though the Table Pointer is 21 bits wide the Program Counter is only shown as 20 bits wide ?

 

[PA3040]

Hi,

Thanks for the reply

Can you please explain the task of Address Latch and Data Latch associate to the program memory

What I cannot see is, though the Table Pointer is 21 bits wide the Program Counter is only shown as 20 bits wide ?

Yes

Please advice

 

[wp100]

Hi,

Its not realistic for me to try and detail all the functionality of an address and data bus and associated control devices, its quiet complicated just to understand an overview let alone detailed circuitry.

You need to do a bit of googling to find such explanations, here is one pdf which shows how a ram chip is addressed and data handled.
https://www.ece.cmu.edu/~ece548/localcpy/sramop.pdf

 

[PA3040]

Hi
Thanks for the reply and information's

This link is very nice and I got lot from it

As per mid- range block diagram the program counter point the locations of the program memory and instruction register is loaded with 14 bit instruction word but in 18F it is some thing different, what do you thing about it

Please advice
Thanks in advance

 

[FvM]

Many points you are asking about are discussed in detail in the PICmicro 18C MCU Family Reference Manual.

 

[wp100]

Hi
Thanks for the reply and information's

This link is very nice and I got lot from it

As per mid- range block diagram the program counter point the locations of the program memory and instruction register is loaded with 14 bit instruction word but in 18F it is some thing different, what do you thing about it

Please advice
Thanks in advance

Hi,

In the early days of micros, the RAM, ROM where separate chips and had to be wired up to work together so you became very familiar with the timings and methods of connection via things like tri state buffers eg 74244 and 74245 chips.

Today no one really bothers with it, as its all done internally to the micro chip and most external communication is done by some serial protocol.


To understand the various sizes of instruction sets / micro families have a look down this page

https://en.wikipedia.org/wiki/PIC_microcontroller

 

[PA3040]

Many points you are asking about are discussed in detail in the PICmicro 18C MCU Family Reference Manual.

Hi
It is nice hear from you and I red the PICmicro 18C reference manual and I could not find it
anyway thanks for information

- - - Updated - - -

Hi,

In the early days of micros, the RAM, ROM where separate chips and had to be wired up to work together so you became very familiar with the timings and methods of connection via things like tri state buffers eg 74244 and 74245 chips.

Today no one really bothers with it, as its all done internally to the micro chip and most external communication is done by some serial protocol.


To understand the various sizes of instruction sets / micro families have a look down this page

You are saying PIC mid-range and PIC 18f are different memory technologies
Please advice

 

[FvM]

I was particularly talking about Section 7. Memory Organization.

 

[PA3040]

Dear All,
Please see the picture attached

while I am reading the memory organization of pic 18f reference manual, I found attached memory block which is unimplemented and external ROM area. Is this area can we connect the external program memory

also mention that micro controller mode ?????/

Please advice

 

[FvM]

A few PIC18 devices allow connection of external program memory, e.g. PIC18F8622 and other 8xxx types.

 

[PA3040]

HI FvM

Thanks for the reply

It would be much appreciated if you can give some idea about Microcontroller Mode in the above picture shows or that mean is it possible in microprocessor mode too?

Please advice
Thanks
Dayan

 

[FvM]

The diagrams from PIC18F8xxx datasheet should clarify the differences between modes. For further details, you should consult the datasheet, I'm not familiar with it.

 

[PA3040]

Dear All,

I found following paragraph from PIC 18C reference manual Memory Organization section of page page 139

7.4.1 Table Reads/Table Writes
Lookup table data may be stored 2 bytes per program word. By using TBLPTR and TABLAT, data
may be retrieved from program memory one byte at a time as required.
Table writes to program memory can be executed as many times as desired. Remember that the
technology of the program memory determines the outcome of the table write. Table writes to
EPROM memory allow the program memory cell to go from a ’1’ state to a ’0’ state, but not the
other direction. FLASH memory allows the cell to go from a ’1’ to a ’0’ and a ’0’ to a ’1’ (though
typically a program memory word or block location is always written).

In the above paragraph I captured following sentence

"Remember that the technology of the program memory determines the outcome of the table write. Table writes to
EPROM memory allow the program memory cell to go from a ’1’ state to a ’0’ state, "

what does efferent this memory technology EPROM and FLASH type program memory?

Pleas advice

 

[FvM]

PIC18C types have EPROM program memory (either one-time-programmable or UV-erasable, requires a package with fused silica window), PIC18F flash memory (reprogrammable).

 

[PA3040]

Dear All,
As per the picture of my first post the table pointer point the content of table in the program memory
as well as program counter point the program instructions in the program memory

My question is, when the table pointer in the action the program counter does not involve .. Am I correct?


Please advice

 

[FvM]

Yes, this are alternative pathes to provide a program memory address. Regular access is through program counter, table pointer is an optional method to read constants or write to flash memory.

 

[PA3040]

Dear FvM Thanks for the reply,

The little things that I have to confirm on the same.

1.Finally The Program Counter and table Pointer are issueing the Program Memory address but not in simultaneously.. Am I correct?
2.In both case instructions are loaded to the instruction register either it is issued by program counter or table pointer
3.In both case the instructions must disassemble by the CPU
4.Table Latch is loaded data ( Instructions ) pointed by Table pointer. Am I correct?

Please advice

Thanks in advance