BANK0 MACRO
bcf STATUS, RP0
bcf STATUS, RP1
ENDM
BANK1 MACRO
bsf STATUS, RP0
bcf STATUS, RP1
ENDM
BANK2 MACRO
bcf STATUS, RP0
bsf STATUS, RP1
ENDM
BANK3 MACRO
bsf STATUS, RP0
bsf STATUS, RP1
ENDM
;-------------------------------------------------------------------------;
; PIC Initialization Routine ;
;-------------------------------------------------------------------------;
PICinit:
; set up ports
; ####### BANK 0 #######
BANK0
clrf PORTA ; init port A
clrf PORTB ; init port B
clrf PORTC ; init port C
clrf ADCON0 ;A2D converter off to save power
clrf STATUS ; clear the Status register
bsf STATUS, IRP ; set IRP for use by FSR in ISR to read Bank3
movlw h'1A' ; load pointer address for CM2CON1
movwf FSR ; store in FSR (in prep for read in ISR)
movlw b'11000001' ; T1G active hi, T1 controlled by T1G, 1:1 prescale, Enable T1
movwf T1CON
movlw b'0111111' ; T2CON postscale = /16, T2 = on, prescale /16 = 15.3 Hz
movwf T2CON
; ####### BANK 1 #######
; set up ports
BANK1
movlw B'01000010' ; Mst PU on, TMR0 uses prescalar at 1:8 ratio
movwf OPTION_REG ; make it so
;PORT A
movlw b'00111000' ; Port A all outputs cept
movwf TRISA ; except RA3,4,5 which are inputs
;PORT B
movlw B'00110000' ; Port B all outputs
movwf TRISB ; except RB4,5 which are inputs
movfw PORTA ; read PortA to resetting IOC latches
movlw b'00110000' ; IOC enabled on RA5 and RA4 - used by encoder
movwf IOCA ; make it so
movlw B'00000010' ; Port C setup, all O/Ps cept C1 = RC in
movwf TRISC ;
; set up timer interrupts
movlw B'00000010' ; enable Timer2 interrupt
movwf PIE1 ; PIE1 bits — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
movlw B'01000000' ; enable C2 interrupt
movwf PIE2 ; PIE2 bits = OSFIE C2IE C1IE EEIE — — — —
; set up oscillator
movlw b'01100001' ; 6:4=110=4MHz, 0=1=Oscillator is internal
movwf OSCCON
; ####### BANK 2 #######
BANK2
clrf ANSEL ; set ports for digital IO
clrf ANSELH
movlw b'00100000' ; set bit 5
movwf ANSEL ; make RC1 an analog input
movlw b'00000000' ; IOC disbled on PortB
movwf IOCB ; make it so
; Comparator set up
clrf CM1CON0 ; disable comparator C1
movlw b'11000101' ; Comp 2 on, inverted, C2out = internal only, C2Vin+ to C2Vref, ip on RC1
movwf CM2CON0 ; make it so
movfw CM2CON0 ; read CM2CON0 to set latch to unset mismatch
movlw b'00000001' ; Tmr1 gate source = SyncC2out, op syncs w falling edge of Tmr1 clk
movwf CM2CON1 ; make it so
movlw b'01001000' ; 0.6Vref goes to C1, CVref cct on routed to C2Vref ip of C2, Hi range...
movwf VRCON ; ..., 0.6Vref disabled, Vref = 2.5 v (make it so)
; ####### BANK 0 #######
BANK0
; Initialize variables
clrf EncoderL
clrf EncoderH
clrf TimeFlags
bcf PIR2, C2IF ; clear Comparator change interrupt
movlw B'11001000' ; GIE + PEIE set to enable peripheral interrupts and
movwf INTCON ; RABIE on
return