1. Explanation about technology:
o Digital design is divided as Front end and Back end. Front end is the area where we design IP without considering the technology node (Ex: 65n, 28n...)
o Once the RTL is ready, we decide the technology. To implement the design IP in particular technology node, we need standard cell and its deliverable in that node.
2. Libraries:
o Libraries contain basic cell like NAND, FLOPS and Boolean functions.
o In Synthesis, RTL a technology independent code is converted into gate level netlist(Specific to the technology node)
3. Place and Route:
o During this process, tool picks the cells from library and place them.
o For placement and routing we need to know the routing data within the cell. This routing info is present in CORE LEF.
o For routing of metal and VIAs we need to have TECHNOLOGY LEF. In this lef pitch and VIAs will be defined considering lpad rules.
o Cells need to be placed considering the timing, this info is present in ".liberty" files.
o ". liberality" files are generated by characterizing the standard cells. Characterization means operating the cells at different load and slew and creating a file with these values. Which will be help full during RTL - GDSII for timing constraints.