When we submit my netlist after DFT to BE Enginer, they want me to provide them SDC file. But I don't know how to produce the file or we should to write it out? And what's the difference between it and top constraint script file? Many thanks!
SDC file is basically the design constraints file. It is used by the physical designer to implement the chip physically. It has to be developed by the logic designer who is the person to know the timing constraints associated with input and output.
Hi
SDC file contains the constraints for Synthesis, Clocking, Timing, Power, Test, Environmental & Operating conditions.It is proven and popular format for describing the design constraints.
Generally BE engineer wants Timing constraints information in SDC format.
You can write the file in the same way as you might have written the tcl file for timing.
SDC is the design constraints fie.
It incorpotares all the constraints for the implementation of the chip (synthesis, place-route, scan insertion etc.) This can be treated as a script file haveing all the constraints fed to the synthesis/implementation/pysical tool. The basic constraints for timing etc must be provided by the designer.
if already implemented a chip, all the constraints can be written out in a .sdc file by write_sdc command in sysnopsys DC.
i hope it helpes