Hi,
Answer to the first question:-
.lib is logical libraries which provide timing and functionality information for standard cells and provide timing information from macrocells
.lef is physical libraries which contain physical information(height,width) of all standard,pad,macro cells
.DEF is design exchange format u will write DEF once u have done analysis with icc u can use the same files in cadance
.tf technology file,technology file is unique to each technology and it contains metal information(like name and number desigination of metallayers/vias,electrical characterstics of metal layers/vias,design rule characterstics of metal layers/vias (wire to wire spacing,wire width),units and precissions,colour and patterns for display
---------- Post added at 16:29 ---------- Previous post was at 16:25 ----------
Hi,
Answer to second question:-
Hard Blockages
revents placing of standard cells near or corner edges of macros completely
soft Blockages:-In soft blockages buffers and invertors are placed for optimization
With Regards,
Raviteja.
---------- Post added at 16:31 ---------- Previous post was at 16:29 ----------
Macro is nothing but it also contains standard cells,standard cells are your basic logic gates(and,or,nand,nor,not,buffer,xor,xnor)
---------- Post added at 16:33 ---------- Previous post was at 16:31 ----------
Wireload models contains parasatic values and are three types
Top,Segamented,Enclosed
---------- Post added at 16:38 ---------- Previous post was at 16:33 ----------
The inputs to your design are
1.logical libraries
2.physical libraries
3.technology files
4.TLU+ files
5.Gatelevel netlist
6.SDC(Synopsys Design constraints)
These are the inputs to your design
---------- Post added at 16:40 ---------- Previous post was at 16:38 ----------
SDC contains clock latancy,clock uncrtainity,input delay,output delay,multi cycle path,false paths,half cycle paths,clock definition