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phase selector verilog-A model

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nichocheng

Newbie level 3
Hi, all:

I need your help. I want to write verilog-A model about phase selector. The phase selector theory is: there are eight phase clock input, and the phase difference is 0.125*2*pi*Fref. I need to select one of them output.
When A=-1, the output is a phase that lag the current one
A=0, the output is current phase.
A=1, the output is a phase lead the current one by two
A=2, the output is a phase lead the current one by one.
I write the verilog-A model like this:

// VerilogA for USB20, PHASE_SELECT, veriloga

include "constants.vams"
include "disciplines.vams"

module PHASE_SELECT(P, IN0, IN1, IN2, IN3, OUT);
output OUT;
input [0:7] P;
input IN0, IN1, IN2, IN3;
voltage [0:7] P;
electrical IN0, IN1, IN2, IN3, OUT;

parameter real tdel = 0 from [0:inf);
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);

real IN;
integer i;
analog begin
@ ( initial_step ) begin
i=1;
IN = V(IN0) + 2*V(IN1) + 4*V(IN2) -8* V(IN3);
end
case (IN)
2: begin if (i-2>=0)
i= i-2;
else i= 8+i-2;
end
1: begin if (i-1>=0)
i= i-1;
else i= 8+i-1;
end
0: i=i;
-1: begin if (i+1<=7)
i= i+1;
else i=-8+i+1;
end
endcase

V(OUT) <+ transition(P, tdel, trise, tfall);
end
endmodule

Whatever I setup the IN0-IN3, the output is zero without any change. Can anyone help me? Thanks.

---------- Post added at 10:04 ---------- Previous post was at 09:32 ----------

My cadence version is 5.10.41, so I can not use "genvar" command.

Maybe it caused by this.

Your block is not sensitive to the input changes and therefore once you finish the @initial_step your block stays inactive. You need to detect changes in the control word and in the input clock and transfer them to the output. You can, for instance, use the function @cross() on your inputs.

Thanks, JoannesPaulus. I don't know how to use a vector P[0:7] as input, indeed. Whether You mean that I need to use cross function instead of if function?
And another question is //V(OUT) <+ transition(P, tdel, trise, tfall);// I want to send P to output, is it right? thanks again.

Last edited:

Verilog-A uses "generate" not "genvar".

If I understand pancho_hideboo's code, he is generating an autonomous clock with a given phase but he is not muxing one of the input phases out.
In my opinion, you need to check for changes of either P or IN and then select the correct output using a case statement.

Verilog-A uses "generate" not "genvar".
Wrong.

"generate" is obsolete.
Currently we have to use "genvar".

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Wrong.
My cadence version is 5.10.41, so I can not use "genvar" command.
"genvar" is used in cadence 6.1

Last edited:

I stand corrected on the versions and all the rest.
At any rate, from the bit of information nichocheng gave I believe he is using an older version of spectre - possibly 4.4.x - with DFII 5.10.x (I had the same set-up at a start-up a few years back).

nichocheng, what what is your set-up?

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