Phase measurement circuit

[curious_mind]

I have two square wave signals A and B. B changes its phase relative to A from 0 deg to 360 Deg. I want a scheme to convert the change of phase to digital outputs with accuracy of 0.05 deg (with tracking rate 1 deg/s). It is observed that A and B are sometimes noisy, carrying high frequency signals. Accuracy needs to maintained under such circumstances. Please suggest various methods to accomplish this. I want all hardware solution.

 

[KlausST]

Hi,

"How" did you try?
--> Every modern - but still simple and cheap - microcontroller should be able to do this.

***********

The XOR followed by an analog LPF should work with analog output. But it needs a DFF to find out which one is leading.
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The XOR with counter creates just glitches when close to zero. (Still needs the DFF) So you know you are close to zero. It's a valid result.
And since your "resolution" is just 2.8us ... I see no problem with glitches in the nanoseconds region.
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Sadly you did not answer my questions above, thus discussion stalled.


Klaus

 

[curious_mind]

When Phase is zero, xor output is zero and when phase difference is 180 deg, output is always one. I want to use xor output to enable the counter and thus measure the counts proportional to the phase change. What am I doing wrong?

 

[KlausST]

Hi,

It´s post#23 and you still give vague incomplete informations but expect us to give you a solution.
How can this work?

We don´t know what counter, what counting frequency, how you reset it, what you expect, what you see....

I give exactly one additional reply, then I leave this thread. So it´s on your informations whether I´m able to give good feedback.

Klaus

 

[danadakk]

Counting freg discussed in post # 17.

I will have an example project today.

You can do this in the SOC I am using, or with CPLD or with discrete logic.

XOR approach probably not an option. Because of .005 degree phase resolution
you would need some high res A/D conversion to get at the V, and precise Vdd
supply for the XOR gate, or a cal loop, not a good solution.....The counter technique
the way to go. Note in the counting case you do need a xtal based clock accuracy
for the counter to achieve your resolution goals.


Regards, Dana.

 

[danadakk]

Klauss picked up on error I had in resolution, I was working problem at .005
degrees, where OP required .05 degrees. So good news is that drops needed
clock rates and counter size. Although we could, if latency not an issue, use
a big counter to acquire a sum of N samples and then average them by simple
shift (divide) of counter result after N samples counted up in counter. N being
a binary power of two value like 2, 4, 8, 16........filtering almost for free

Regards, Dana.

 

[danadakk]

This seems to be working, but have not tried the dead band, Note I ran out of time
to implenet the averaging with the counter, but that should be minor implementation.

Regards, Dana.

--- Updated Feb 16, 2023 ---

When Phase is zero, xor output is zero and when phase difference is 180 deg, output is always one. I want to use xor output to enable the counter and thus measure the counts proportional to the phase change. What am I doing wrong?

You could try the D solution for the phase detector, incoming Fref and Fx go to the set, preset, of the flop,
D = 1, and clock set to gnd, or use dual Ds or the bang bang phase detector.

Just tried the deadband at 0 and mine generates 0 degrees result.

Regards, Dana.

 

[danadakk]

This has dead band phase fix -

https://etd.ohiolink.edu/apexprod/rws_etd/send_file/send?accession=osu1268184406&disposition=inline

Regards, Dana.

 

[FvM]

Required resolution of 0.05° corresponds to about 3 us at 50 Hz. There should be no real dead band problem.

 

[danadakk]

The concern, as expressed in post #20, is really the issue with a 180 degree phase comparator, like XOR exhibits, at 0 ^o and 180 ^o, the output same w/o logic to detect. No matter what the clocking rates are. The width of the region is, however, a f() of clk rate. That was reason for recommending a higher clk rate, 720 Khz, but still leaves the dead band problem to solve, eg. What phase quadrant are we in. And of course the +/- 1 count problem.

This shows the introduction of fixed delay to always force a minimum out of the detector, depending on circuit choosen. Interesting discussion on attributes of common Phase Detector solutions.

https://people.engr.tamu.edu/spalermo/ecen620/lecture04_ee620_phase_detectors.pdf



Regards, Dana.