Continue to Site

# Phase measurement circuit

Status
Not open for further replies.

#### curious_mind

##### Full Member level 4
I have two square wave signals A and B. B changes its phase relative to A from 0 deg to 360 Deg. I want a scheme to convert the change of phase to digital outputs with accuracy of 0.05 deg (with tracking rate 1 deg/s). It is observed that A and B are sometimes noisy, carrying high frequency signals. Accuracy needs to maintained under such circumstances. Please suggest various methods to accomplish this. I want all hardware solution.

Hi,

I did an internet search for: "circuit phase two square waves".
--> Plenty of good solutions.
I guess you´ve done this before. So what is the exact problem with all the shown solutions?

You give just vague and incomplete informations. For sure it is a big difference whether this circuit is for mains frequency or gigahertz.
Square wave always contain high frequency, That´s their nature. Mathematically infinite high frequencies.
No idea whether you talk about voltage noise or phase noise.
Voltage levels?

Klaus

oops. Forgot to mention the frequency. A and B are both 50Hz. I am not sure if PLL is better or using classical time to digital converter based on start/stop signal reference for A and B

Hi,

please refer to a circuit ... or at least an internet site.

0.05° at 50 Hz is about 2.8us. Where is the problem?

Klaus

You want 1 deg / s tracking rate, and the need to average / filter the signals to get
rid of noise / jitter seems challenging, eg meting latency of measurement.

One thinks of reciprocal counting technique applied to the signals, and averaging those.
Counter accuracy would have to be something like 360 / (.05 / 2) implies ~ 14 bit counters.
Clocked at 14 Khz or better.

Regards, Dana.

should we use a pll to eliminate noise and then user frquency counting technique to determine the phase?

Hi,

No circuit, no link to a web page, not even a simple sketch.

Klaus

Hi,

e.g. a simultaneous sampling ADC

BR

should we use a pll to eliminate noise and then user frquency counting technique to determine the phase?
Yes you could consider PLL. Its acts as integrator on front end, has advantage takes out
jitter (to a point), but you pay for it in latency and step resposne. You trade off loop
BW response and noise rejection.

Or you average a sample set on back end. Eliminating PLL.

I would choose PLL if front end noise can otherwise cause counting issues for digital
logic.

Regards, Dana.

Are there any digital PLLs that take 50hz input?

Here is an approach using a custom component in this SOC. The SOC is a PSOC 5LP
family part. In PSOC nomenclature a component is an onchip resource. Users can,
and have, created a rich library of components in addition to the standard library
device can draw from, as shown below. Note multiple copies of many of the components
available. This SOC has ARM M3 core in it, there are versions that are dual core as well.

The project using this, again a single chip SOC, looks like :

The datasheet for the component :

http://file.elecfans.com/web1/M00/5B/49/pIYBAFtt0IuAKocVAB11MMg1S8A541.pdf

If you go to the bottom you can see some various configs, showing down to 10 Hz lock.

The IDE, PSOC Creator, and compiler free, good board to start with \$ 15, CY8CKIT-059.
Note board has 2 PSOCs on it, one for debug/program, the other is target. When you
are finished you snap off the debug/program side, and use it for other programming/
debug work. It also can be stand alone application SOC but is severely limited in its I/O
as only pins brought out are the ones for debug/program.

Note the right hand window shows resources used/left in SOC, still tons left for other tasks.

Regards, Dana.

Last edited:

Can we use 74HCT297? Can anybody share their experience using it?

Get one and try it out ....

Primary concern is jitter, loop gain for your application, 2N, where
N = 1 for your application, quite low. A discussion of jitter :

Also loop G controls phase error, not sure what your target is for that.

Regards, Dana.
--- Updated ---

Of course phase error a f() of loop filter :

Regards, Dana.

Last edited:

I have spelt my requirement in #1. What about just using a phase comparator?. I do not require any phase locking. I only need to estimate phase difference between the two square wave signals. The only concern was the jitter and noise overriding the square wave.

Without a loop filter you will have very large jitter.

Regards, Dana.

So can I understand that for effective phase measurement, I need to go for a PLL with integrated VCO+loop filter and close the loop with a N bit counter.
All I need is to measure frequency of VCO to determine phase. Please clarify. Also VCO with 4046 PLL is having temp coeff. of 600 ppm/deg c. Can we have alternate method of generating highly linear freq output with high temperature stability

If you are sure the 50 Hz waveforms same freq (otherwise use PLL approach) you can consider this :

The notes shown above, below the circuit, explain operation. Note effectively the counter
is acting as a reciprocal counter in this design.

You could take multiple measurement samples and average them, that causes additional
latency but reduces jitter in measurement. Also I would use this approach and add the onchip
DMA facility to DMA the samples into memory for averaging after sample set has accrued.

This of course can also be done in Verilog on this SOC for a complete HW solution.....

Regards, Dana.

Last edited:

So can I understand that for effective phase measurement, I need to go for a PLL with integrated VCO+loop filter and close the loop with a N bit counter.
All I need is to measure frequency of VCO to determine phase. Please clarify. Also VCO with 4046 PLL is having temp coeff. of 600 ppm/deg c. Can we have alternate method of generating highly linear freq output with high temperature stability
From Gardner the phase is :

On review looks like the steady state phase error is driven to 0 over time, and loop
G and filter determines response to step input. So non steady state constant phase error
only occurs per above table.

So in short the solution posted earlier with counter probably best approach to determining
phase error. And averaging to remove jitter. Note you can get instantaneous phase out of
that method, but that can have substantial jitter cycle to cycle unless the input signals are
themselves have very low rates of change.

OR you can just use the phase detector, convert its output to V, and measure that.

Regards, Dana.
--- Updated ---

Note I am waiting on a sim company to provide me answer, trying to sim
a simple phase detector and output filter.

I will post once I get answer.

Regards, Dana.

Last edited:

Falstad's animated interactive simulator has a built-in library of circuits including PLL's of different topologies.
One of them depicts the internals of a phase comparator.
Another is an XOR gate revealing the amount of overlap between two square waves.

Free to download and use. (Requires Java installed on your computer.)

falstad.com/circuit

I have tried the counter circuit. But it turns out that when phase is zero, both the input signals edges coincide creating a dead band , which cannot be resolved either by XOR gate or SR FF . Should we delay one signal to avoid this? Any good commercial phase comparators to work with 50hz frequency?

Status
Not open for further replies.