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Phase Locked Loop (PLL) Lock Range

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qwaszxpolkmn

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Hi,

I've got a project and would like to design a PLL. I was wondering how I can increase the lock range of the PLL and what parameters do affect its lock range?
Are there any equations for calculating this range?

Thank you in advance for your responses.
 

The lock range depends, among other things, upon the type of phase detector used.

A XOR type phase detector has a limited lock range depending upon several variables including the control loop frequency response and the VCO range.
And when locked there can be a phase difference of up to ±90° between the input and the VCO signal.

A digital Phase-Frequency Detector however, will lock into any frequency within the frequency range of the VCO.
When locked it has a phase-difference of zero degrees between the input and the VCO signal.
It's disadvantage is that it may not work as well with a noisy signal as an XOR circuit.

The CD4046 PLL/VCO IC, for example, contains both of these types of phase detectors.
 
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    FvM

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Thank you guys.

We have used a mixer as a phase detector.

-Could low pass filter on the output of the mixer affect the lock range?
-Is there a trade-off between loop gain and lock range? (I mean is it possible to have a better lock range by increasing the loop gain?)
-Are there any design techniques to improve the lock range?
 

There is a non-linear effect of Loop BW on Capture range and lock-in time.
THe error signal in f must be within the loop bandwidth.

Using CMOS analog switches , one can change the bandwidth after locked as long as an offset is not induced or a large transient pF pulse discharge. Or one can use a linear AGC approach to change bandwidth smoothly.

All mixers are phase detectors and all phase detectors are mixers unless phase/frequency type II digital mixers, which have full capture range.
Down side is they have more phase noise locked on rising edge and some dead-time, instead of averaging types that lock on at 90deg, but total lock-in range.

Gain affects stability, phase margin and capture time and a lag-lead filter is essential C1//R+C2 where C1/C2 ~10:1 typ.
 
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