Persistent Verilog-A variables for co-simulation with H-SPICE

[pizzadoe]

I'm trying to write verilog models to implement optical components in SPICE simulations, using HSPICE as the simulator. The issue is these models will require variables to persist over multiple steps in the SPICE simulation, and it currently seems that H-SPICE instantiates and destroys the model at each time step, so the variables are lost. Is there any simple way to make this data persistent?