PCI + FPGA Interface... Clock

[Sink0]

Hi i have couple questions about creating a PCI - FPGA Interface..

First.. is it mandatory to feed FPGA with PCI clock? Is PCI clock 33Mhz or 100/3Mhz (33.3333....Mhz)?

If i feed FPGA with 2 clocks, PCI clock and some other one to run other blocks, which problems am i going to have to make blocks feeded by each clock to talk?

Thank you!

 

[permute]

For a multi-clock design, you will generally use FIFO's to send data between each clock domain. for simple status, you might use "synchronizers", or two registers in a row. This makes it very unlikely (like once every billion years) that a metastable value will be passed to the other clock domain.

If the clock domains are related, eg 266...MHz and 33...MHz, then you can simply tell the tools this and allow them to ensure setup/hold times are met. you may have some issues with skew though, if the 33MHz and 266MHz are not synthesized by the same synthesizer (PLL/DCM/MCM). You should read the clocking section of the relevant user's guide for more info.