You are correct. that is for outer layer of PCB. For traces running on internal layers this clearance will be lower. With conformal coating on the outer layer, the clearance will also come down.
For quick reference check this out. https://www.smps.us/pcbtracespacing.html
It has embedded calc in the webpage.
What market is it going in, what sort of equipment is it...
Main standard for most electronics is 60590 (prefix depend on region)
More info here: https://www.edaboard.com/threads/330347/
What market is it going in, what sort of equipment is it...
Main standard for most electronics is 60590 (prefix depend on region)
More info here: https://www.edaboard.com/threads/330347/
If you have the room for it on the board, then choose the clearance far higher than the minimum. Cracks in the board caused by temperature shocks or excessive stress may reduce insulation effectiveness over time.
So it not going to be in very harsh conditions... Will have to re-read the spec to get pollution level
If the board develops cracks you are going to be the unluckiest designer in the world.... because it would be the layer to layer clearances that would be affected and if you have high voltages then the design should be done so that cracks etc. do not appear or your design is dangerous..... never had that problem myself.