High current------> Thick track------> Avoid thermal relief as much as possible. Make all connections solid. If you have to use thermal relief, the sum total of the spoke width should confirm to the required trace width.
For 5A/ 1Oz board, use 300mil on inner and 150mil on outer layers
For 5A/ 2Oz board, use 150mil on inner and 60mil on outer layers
Hi dunn,
usually I make PCB with Hi Current ( 5A to 13A ) and I don't use Thermal Relief
on component pins (Connectors,Relays....)
On production (~ 30.000 pz for year) I seen that the pins howhever had a good solder.
Ok, all understood about NOT to use Thermal Relief.
How is it ensured that the component (High current - see above post) will not get damaged in the soldering process?
(That is, heat is applied to the pad, the copper conducts the heat away (due to no Thermal Relief) more heat is applied, and component gets damaged due to excessive heat)?
Required trace width and copper thickness can be defined by taking the resistive losses in account and also see how much the temperature rise will be. There are several nomograms available on the internet.
You may also want to consider CAD-software that supports pads with multi-drill (plated) via holes.
It is quite common to see high current designs using wide traces and thick copper, but where the thru-hole vias consists of one single hole.
One CAD-software that I know of that can define multi hole pads is Cadence Allegro. This product is also available in some sort of "lite"(?) version as "PCB Editor" in a low cost version.
(There must be others of course and I do not in any way claim that Allegro should be the only one)
Otherwise the cad engineer will have to place multiple vias manually....
https://www.diptrace.com/ is available in a freeware version (250 pin limit) and supports multiple layers, schamatic capture and auto routing.) One can have Cu Pours that is a part one of the nets.
However it's bus to track conversions does not create tracks of equal length.