PC PCI interfacing with uC

[Rohith_elec]

I would like to interface a PIC microcontroller with the PCI interface of PC. what should be the starting place for it ?

 

[bigdogguru]

In other words, you would like to design a PCI card with a PIC onboard? :shock:

Why?

If this is the requirement, you would need to either utilize an existing PCI interface chipset or implement such an interface with an FPGA/CPLD.

Implementing a PCI interface is certainly a nontrivial affair.


BigDog

 

[Rohith_elec]

By PCI interface chipset , you mean the chipset already on the board ?

 

[Jestin_cubetech]

https://en.wikipedia.org/wiki/Conventional_PCI


in Side B Side A Comments
1 −12 V TRST# JTAG port pins (optional)
2 TCK +12 V
3 Ground TMS
4 TDO TDI
5 +5 V +5 V
6 +5 V INTA# Interrupt lines (open-drain)
7 INTB# INTC#
8 INTD# +5 V
9 PRSNT1# Reserved Pulled low to indicate 7.5 or 25 W power required
10 Reserved IOPWR +5 V or +3.3 V
11 PRSNT2# Reserved Pulled low to indicate 7.5 or 15 W power required
12 Ground Ground Key notch for 3.3 V-capable cards
13 Ground Ground
14 Reserved 3.3 V aux Standby power (optional)
15 Ground RST# Bus reset
16 CLK IOPWR 33/66 MHz clock
17 Ground GNT# Bus grant from motherboard to card
18 REQ# Ground Bus request from card to motherboard
19 IOPWR PME# Power management event (optional) 3.3 V, open drain, active low.[10]
20 AD[31] AD[30] Address/data bus (upper half)
21 AD[29] +3.3 V
22 Ground AD[28]
23 AD[27] AD[26]
24 AD[25] Ground
25 +3.3 V AD[24]
26 C/BE[3]# IDSEL
27 AD[23] +3.3 V
28 Ground AD[22]
29 AD[21] AD[20]
30 AD[19] Ground
31 +3.3 V AD[18]
32 AD[17] AD[16]
33 C/BE[2]# +3.3 V
34 Ground FRAME# Bus transfer in progress
35 IRDY# Ground Initiator ready
36 +3.3 V TRDY# Target ready
37 DEVSEL# Ground Target selected
38 Ground STOP# Target requests halt
39 LOCK# +3.3 V Locked transaction
40 PERR# SMBCLK SDONE Parity error; SMBus clock or Snoop done (obsolete)
41 +3.3 V SMBDAT SBO# SMBus data or Snoop backoff (obsolete)
42 SERR# Ground System error
43 +3.3 V PAR Even parity over AD[31:00] and C/BE[3:0]#
44 C/BE[1]# AD[15] Address/data bus (lower half)
45 AD[14] +3.3 V
46 Ground AD[13]
47 AD[12] AD[11]
48 AD[10] Ground
49 M66EN Ground AD[09]
50 Ground Ground Key notch for 5 V-capable cards
51 Ground Ground
52 AD[08] C/BE[0]# Address/data bus (lower half)
53 AD[07] +3.3 V
54 +3.3 V AD[06]
55 AD[05] AD[04]
56 AD[03] Ground
57 Ground AD[02]
58 AD[01] AD[00]
59 IOPWR IOPWR
60 ACK64# REQ64# For 64-bit extension; no connect for 32-bit devices.
61 +5 V +5 V
62 +5 V +5 V

 

[bigdogguru]

By PCI interface chipset , you mean the chipset already on the board ?

There is a chipset on the motherboard which forms a bridge between several other interfaces, the local bus and the CPU.

And each PCI card requires an bridge/interface chipset or FPGA/CPLD implementing the proper core to handle auto configuration (plug-n-play), configuration space, control (interrupts/timing/latency), data/address and other interface logistics.

You'll see the term "bridge" mentioned quite often when reading PCI related documentation, the term simply refers to the transfer of data from interface/bus standard to another in an orderly controlled fashion.

An example of a manufacturer of both such chipsets:







The PCI interface is certainly one of the more complex interfaces, which is why many applications have migrated to USB or PCI Express (PCIe).

If you desire to interface a PIC to the PC via a "card" you may wish to consider the ISA bus, if you have a PC which still offers this interface standard.

While the ISA bus still requires some interface "glue" logic, it is by no means as complex as the PCI bus standards.

And of course, there is always the more recent USB interface.

Also, I cannot stress this fact enough, when developing any type of interface card always use a PC which can be sacrificed if damaged.

Do not use your primary PC as a development platform.

BigDog