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[PIC] pb with vinculum controler and pic 18f4450

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Newbie level 6
Aug 22, 2011
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The pic 18f4450 and the vinculum vnc1l controller are connected via the spi interface like this (signals are in the point a view of the pic):

clk => rb1 - output
cs => rb2 - output
sdi => rc7 - input
sdo => rb4 - output

I connect my logic analyzer to these signals to see what is happening and i discover glitches on the "cs" signal (look at the picture between G1 and G2 markers) and on the "di" signal which is the "sdo" signal of the vinculum.

is-it normal ?



glitchs on cs.jpg

Without seeing your code it is very hard to tell.
The normal configuration is for the PIC to be the master and the VNC1 to be the SPI slave (in fact I seem to remember that the VNC1 can only be the slave) which means that the PIC is the device that is generating the CS signal (as well as the SCK).
Therefore, if there are glitches on the CS line then they are either coming from the PIC or there is something else on the line that is trying to drive the line. When properly configured to use the SPI interface, the VNC1 should not be driving that line itself.
As the VNC1 uses a 13-bit transfer, I assume that you are bit-banging the SPI master interface (as the PIC18F SPI hardware uses 8-bit exchanges).
What also concerns me from your picture are the clock pulses that are being generated when the CS line is low (they should be ignored but why generate them); why are the clock pulses not evenly timed (especially right at the left-hand and right-hand edges of your picture - again the VNC1 should only use the rising clock edge but this does look unusual to me), and also the glitches all through the picture on the DI line on mainly the trailing clock edge but also the leading clock edge in some cases.
All of this would seem to indicate a very noisy environment (perhaps a poor power supply???) with lots of cross-over between the SPI signals. Try looking at the signals in "analog" mode and I suspect you will see a lot of noise that is enough to trigger the 'digital' mode logic analyser into making the transitions.
Are you using a breadboard? They are notorious for high levels of capacitance (and hence coupling) between the tracks, especially when higher frequencies are involved.
The simply answer to your question is "no - it is not normal".


Yes, i used a breadboard to test my software and that was the cause of the glitches.

I didn't thought this could cause problems at these frequencies.

I directly soldered the vdip1 module which containt the vnc1l chip on my developpement board and the glitches disappeared.

For the clock, it is normal that the duty cycle is not 50%: the clock is generated by software and i use the low state to put the data on the "do" pin which require some additional cpu cycles (on the waveform you see the pic sending an echo command to the vnc1l chip).



cs free of glitches.jpg

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