willycat
Newbie level 6
Hi,
The pic 18f4450 and the vinculum vnc1l controller are connected via the spi interface like this (signals are in the point a view of the pic):
clk => rb1 - output
cs => rb2 - output
sdi => rc7 - input
sdo => rb4 - output
I connect my logic analyzer to these signals to see what is happening and i discover glitches on the "cs" signal (look at the picture between G1 and G2 markers) and on the "di" signal which is the "sdo" signal of the vinculum.
is-it normal ?
Thanks,
Willy.
The pic 18f4450 and the vinculum vnc1l controller are connected via the spi interface like this (signals are in the point a view of the pic):
clk => rb1 - output
cs => rb2 - output
sdi => rc7 - input
sdo => rb4 - output
I connect my logic analyzer to these signals to see what is happening and i discover glitches on the "cs" signal (look at the picture between G1 and G2 markers) and on the "di" signal which is the "sdo" signal of the vinculum.
is-it normal ?
Thanks,
Willy.