[SOLVED] Partially depleted SOI (silicon on insulator)

[astroshey]

Why is a partially depleted SOI called "partially depleted" SOI. I have heard people responding "well, because it's partially depleted". But I still dont fully understand. Is it partially depleted to begin with or when a certain Vg is applied only part of the body gets depleted. Thanks for the help.

 

[dick_freebird]

Fully depleted is a declaration that, at Vgs=0, the depletion
layer below the gate ezxtends to the BOX. Now many people
seem to think this is true all across the bias ranges of gate,
body, source, drain but it is not. There are regions (like near /
subthreshold) where the inversion sheet shields the body
pocket and leaves it to float, if silicon layer is thick enough.
Then you get things like kink and RTN to play with. FDSOI
film thickness is hundreds of nm.S, D junctions will bottom out
so no bottom plate capacitance / nonlinearities. Coff is improved
big time and remaining capacitances become more linear
(oxide dominated). Body ties are ineffective when the inversion
sheet begins to form, blocking ohmic path to the channel root
from the P+ tap. May still be effective at Vgs=0 logic leakage,
but not for kink suppression etc. FDSOI fanboys will argue
that there is no kink. They lie. You just have to know where to
look, and low power analog designers live there.

When you get to thicker films the Vgs / Vbs=0 depletion
under gate cannot reach the BOX. Typically neither will your
S, D implants. So you pick up junction terms of Csb, Cdb
with their nonlinear capacitance & current. So inferior for RF
harmonics, intermodulation. But much superior for baseband
analog (no back gate, kink, RTN) and often you can use the
same MOS models as the JI root flow (Cbs, Dbs aside - and
those are "deletes"). You also can add an -effective- body tie
/ tap

The final question, whether depletion-of-body changes with
Vgs / Vgb, is "yes" (explanations above). People like to make
"fully depleted" mean more than it specifically does, wanting
to believe in idealities.

 

[astroshey]

Thanks for the explanation.
First: Could you please similarly explain PDSOI and why it's calls "PD"?
Second: you mentioned, "Fully depleted is a declaration that, at Vgs=0, the depletion
layer below the gate ezxtends to the BOX" -- So, this depletion layer is depleted of free majority carriers and is just comprised of impurity ions at Vgs? Because that's what it means by "depletion" in bulk CMOS. Please let me know, thanks for the help!