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Parasitic Diodes in Post-Layout Simulation

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Newbie level 6
Jul 27, 2011
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I am working on the design of a delay-line ring oscillator which is composed of three differential delay stages as shown in the pic. My center frequency in the schematic design is 1GHz. I laid it out and got the extracted view. The post-layout simulation gave me a much slower performance (750MHz center frequency). I've looked at the netlist for the extracted circuit, and saw that parasitic caps, resistors, and diodes were added after the extraction. I tried to put the same size caps and diodes into the schematic to check which one caused the problem and found that the parasitic caps are really small and did not affect the performance. However, once the parasitic diodes are added at outputs of each delay-stage (it is where they are in the extracted view), my oscillator starts to get slower.

Is it because the reverse biased parasitic diode capacitance makes the circuit work much slower since the outputs of each delay stage is suppose to be the high speed lines? If that is the case, is there any method to minimize this diode parasitic in the layout?

Many thanks,


Can you set the n-wells to a higher voltage?

And if you have a double/triple well process, can you set the p-well in n-well bulks to a voltage higher than substrate?

Transistor source (= main diodes) sizes minimized?

I'm curious why parasitic diodes are not part of the active
devices, from the get-go? Certainly D-B and S-B diodes
should be. The only post-layout thing I can imagine is
antenna diodes, which I'd think ought to be placed in the
schematic (if you're going at it analog style and not auto
routing, at least).

It's my experience that any junctions that are an integral
part of a transistor, get modeled within the transistor (at
compact model level, or within subcircuit) even in schematic
design environment.

Where do these parasitic diodes come from?

Indeed, it is very strange to hear about parasitic diodes added to the extracted netlist or extracted view - usually, only parasitic C, or R and C elements are added...

On the other hand - at the schematic level, the geometric parameters of the parasitic diodes - AS, AD, PS, PD, etc. - are not known.
Does circuit simulator or compact models assume some default values? or set them to zeros?
These parameters are extracted from the layout...

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