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Parasitic capacitance of MIM capacitor

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guow06

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I can just find the bottom parasitic capacitance value in design_manual. What's that typically for the top plate?
I am designing a SAR ADC, I am wondering whether the parasitic capacitance or the mismatch is more important.
 
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timof

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I can just find the bottom parasitic capacitance value in design_manual. What's that typically for the top plate?
I am designing a SAR ADC, I am wondering whether the parasitic capacitance or the mismatch is more important.

Mismatch between neighboring capacitors can be caused by:

1. (uncontrolled) random variations cased by microscopic process effects - this is non-systematic mismatch

2. by layout - i.e. by difference in parasitic capacitances - which is systematic mismatch.

Which one of these components is larger depends on several factors - for example, on layout style, on capacitor size (the larger the capacitor, the smaller the random mismatch - it usually scales as 1/sqrt(A), where A is the device area), etc.

To minimize random mismatch, (intended) capacitor size should be made larger.
Large capacitors usually also help minimize the impact of parasitics.
(the downside of large capacitors is large chip area (cost), large dynamic power consumption (CV2f), etc.).

Systematic mismatch, caused by parasitics (due to layout differences), can be characterized using high-precision parasitic extraction tools (field solvers).

You can find discussions in this thread relevant:

https://www.edaboard.com/threads/159589/
 
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