xihuwang
Member level 2
pll question set
Hi, every one :
I am design a pll with below requeriments and specs :
1. It will be used in a soc . For area requeriment, the cap used
in LF should be no more than 100pF
2. The input reference frequency will be 6-12MHz
3. The output reference should be above 200MHz
4. The peak-to-peak jitter , I think should below 0.2ns under all PVT
5. A 0.35um CMOS process under development (SOI process but using H
gate, so the gate cap is terrilbly big for small W/L transistor).
6. There is no spice model now for the process.
My questions is :
1. Based on your experices, what is the range of VCO under 0.35um process
2. What is the charge pump current , below 5uA?
3. sync or async frequency divider ?
4. For no spice model now, I am worried about the frequency stability for
the loop gain variation. So how can I guaratee the stability ?
Added after 45 minutes:
5. What is the bandwidth should be set ? Is 200kHz too big for decreasing jitter ?
Hi, every one :
I am design a pll with below requeriments and specs :
1. It will be used in a soc . For area requeriment, the cap used
in LF should be no more than 100pF
2. The input reference frequency will be 6-12MHz
3. The output reference should be above 200MHz
4. The peak-to-peak jitter , I think should below 0.2ns under all PVT
5. A 0.35um CMOS process under development (SOI process but using H
gate, so the gate cap is terrilbly big for small W/L transistor).
6. There is no spice model now for the process.
My questions is :
1. Based on your experices, what is the range of VCO under 0.35um process
2. What is the charge pump current , below 5uA?
3. sync or async frequency divider ?
4. For no spice model now, I am worried about the frequency stability for
the loop gain variation. So how can I guaratee the stability ?
Added after 45 minutes:
5. What is the bandwidth should be set ? Is 200kHz too big for decreasing jitter ?