parameter set for a pll design

[xihuwang]

pll question set

Hi, every one :
I am design a pll with below requeriments and specs :
1. It will be used in a soc . For area requeriment, the cap used
in LF should be no more than 100pF
2. The input reference frequency will be 6-12MHz
3. The output reference should be above 200MHz
4. The peak-to-peak jitter , I think should below 0.2ns under all PVT
5. A 0.35um CMOS process under development (SOI process but using H
gate, so the gate cap is terrilbly big for small W/L transistor).
6. There is no spice model now for the process.
My questions is :
1. Based on your experices, what is the range of VCO under 0.35um process
2. What is the charge pump current , below 5uA?
3. sync or async frequency divider ?
4. For no spice model now, I am worried about the frequency stability for
the loop gain variation. So how can I guaratee the stability ?

Added after 45 minutes:

5. What is the bandwidth should be set ? Is 200kHz too big for decreasing jitter ?

 

[xihuwang]

6. Another question puzzle me is :
The output of last stage of VCO must not only drive the 1th stage but also
the differential amplifier ( used to convert the differential small swing output
of VCO to full swing single-ended signal) . So the last stage of the VCO will
has larger delay than the other stages .
Does this involve big jitter . If so , how to conquer this ?

 

[flatulent]

As far as the bandwidth there are two criteria. Use the lower of the two below:

1. It is where the phase noise of the reference is equal to that of the VCO.
2. It should be 1/10 of the reference frequency or less.

 

[xihuwang]

Thanks for help .

I have another questions :

8. I designed 3 charge pump. The 3 CP are connected or disconnected
with the same LPF by pass gate to check the performance of CP.
My question is wheather the pass gate's resistor and parastic cap
will decrease the pll's performance

9. For a normal crystal oscilator (4-12MHz) , what are the jitters ?

 

[xihuwang]

10 , how to design the I/O and pad , ESD of the pll out signal ?

 

[xihuwang]

11. If the VCO's ability to start to oscilating should be considered ?