A behavioral model is not going to help you identify a timing problem, you'll need a TIMING model. But, since you can't find either, you're going to have to take a different approach. You should be able to resolve this just using Chipscope. Looking at the actual hardware is better than a simulation anyway. Looking at this chip's data sheet (briefly), I can see that you need to make sure that aside from your address and data lines, you need to make sure your ADV, CE, OE, RST, WE and WP signals are in the proper state. Have you also verified your power supplies? Is your WP pulled high? Do you have any unused outputs on your CPLD that you can use to bring signals to so you can hook up a logic analyzer or scope? (In my designs I usually have 16 pins or so tied to a header that I can use for debugging for just such situations you are experiencing.)
Don't give up yet!