Parallel Prom Behavioral Model

[zorax85]

I'm getting crazy with a Prom memory. I'm trying to interface it at an FPGA, using a controller implemented inside a CPLD. However I've found ambiguous information on the datasheet, and using Chipscope, I saw that I'm so far away from my goal. Because of that I would like to find a Behavioral Model of that Parallel Flash PROM, in order to perform a good simulation. Has anyone an idea about where can I found this model? Other suggestions?

Model: PC28F00AP33EFA
Manufacturer: Numonyx
Datasheet: **broken link removed**

Thanks

 

[barry]

Look on the manufacturer's website; that's the only place you're going to find a model. You might contact their tech support for more help.

However, without knowing more, I suspect that getting the model is not going to solve your problem. You obviously have a flaw in your design and simulating the model is just going to fail like your Chipscope analysis. Go back and verify that your signals to the prom are what the spec requires. Put a scope on your board and verify the signal levels and timing (hopefully it's not a BGA). Maybe write a simple program that just reads and writes to the prom; get the rest of the junk out of the way so can verify the fundamental operation of the prom; this also will free up a lot of your CPLD resources for chipscope to use.

Also, do you know if the problem is in your CPLD or FPGA? If you haven't isolated it to that level, then that's the FIRST thing you should do.

Good luck.

Barry

 

[zorax85]

I've already done all you suggested. Nothing on the manufacturer's web site, and no answer from their tech support. This Prom is it just a BGA and the issue about I'm in trouble, it's in the "simple" read/write operation

I mean, if I can use a behavioral model, provided by a feedback signal, normally I can look at wich operation I'm doing, if I'm not respecting timing requirements, etc... It could be useful.

 

[barry]

A behavioral model is not going to help you identify a timing problem, you'll need a TIMING model. But, since you can't find either, you're going to have to take a different approach. You should be able to resolve this just using Chipscope. Looking at the actual hardware is better than a simulation anyway. Looking at this chip's data sheet (briefly), I can see that you need to make sure that aside from your address and data lines, you need to make sure your ADV, CE, OE, RST, WE and WP signals are in the proper state. Have you also verified your power supplies? Is your WP pulled high? Do you have any unused outputs on your CPLD that you can use to bring signals to so you can hook up a logic analyzer or scope? (In my designs I usually have 16 pins or so tied to a header that I can use for debugging for just such situations you are experiencing.)

Don't give up yet!

 

[zorax85]

Finally I found a behavioral model with some examples and a feedback line on wich I can receive information about what I'm doing. In this way I understood definitively how this prom works, and more or less I've been solved all my problem, now I have just to fix last issues and be sure that I'm respecting the timing requirements.