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Verilog on-line course - question related to behavioral model description and synthesis.

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Advanced Member level 1
Dec 16, 2017
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I am learning Verilog from on-line video course - here is link to part 11 of this course:

Eleven lesson is starting from giving full behavioural model of 16 bits adder (with carry and few flags like zero, parity etc.). Here is code for 16-bit adder (behavioral description):

module 16bitAdder(X, Y , Z, Zero, Carry, Parity, Overflow)
  input[15:0] X, Y;
  output[15;0] Z;
  output Zero, Carry, Parity, Overflow
  assign {Carry,Z} = X + Y;
  assign Sign = Z[15];
  assign Zero = ~|Z;
  assign Parity = ~^Z;
  assign Overflow = (X15]&Y[15]&~Z[15]) | (~X15]&~Y[15]&Z[15]);

I fully understand this code. In next steps this behavioral description is replaced by hierarchical description with more "low level" models until to description made only from basic gates. There also is written a test-bench for this 16-bit adder. It is shown that on low level (gates level) this adder can be implemented as "Ripple Carry Adder" which is slow (O(N)) or "Look Ahead carry Adder" which is fast (O(1)), but more complicated. In this moment it come to my mind a question: Let's assume that in our design in Verilog (in "Synthesis Software" - for example Xilinx Vivado) we only entered this behavioral description of 16-bit adder (the given Verilog code for module "16bitAdde"), I am curious what it will be generated by synthesis software: a version of "Ripple Carry Adder" or most advanced and faster "Look Ahead Adder". The second question is: Could designer inform "synthesis software" how to generate low-level description of such module (16-bit adder), maybe by use of Verilog directives? It is also interesting for me: How it is with another behavioral models of arithmetic circuits (for example multiplication circuit, etc.) Can DSP blocks from FPGA be used for default for such high-level descriptions of modules?

Thanks in advance and Regards

FPGA synthesis software is quite good in optimizing arithmetic problems, it's specifically designed to do so. Thus just entering a behavioral description will achieve a good result in most cases. DSP modules are utilized by default.

Writing your own low level modules may be useful for eductational purposes but is unlikely to achieve optimal results because it doesn't make use of hardware features like fast carry chains.

Review the tools manual how to control implementaion with synthesis attributes. Do your own experiments, compare different implementations in RTL and gate level viewer, look at resource utilisation and timing analysis results.
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