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Parallel blocks in Verilog

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Arik

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sequential and parallel blocks verilog

Hi

What's the difference between parallel block and a sequential block with non-blocking assignments ?

In other words is there any parallel functionality that could not be implemented with non-blocking assignments inside sequential block and requires a parallel block ?


thanks and regards
 

avimit

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parallel block in verilog

Hi,
1. In principle you can do all sort of parallism using only blocking or only on blocking assignments.
2. parallel blocks? what are you trying to refer to? I guess you are referring to the 'assign' statements? or you are referring to say 2 always blocks or 2 initial blocks or a mixture of two? pls specify
sequential blocks: I guess you are refering code written inside 'initial' or 'always' blocks?, Again you can have all kind of parallelism using either blocking or non-blocking assignments. However it may not be the recommended way of doing things.
Dunno if I have got you right, if not pls elaborate
Kr,
Avi
https://www.vlsiip.com
 

Arik

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sequential and parallel blocks in verilog

thx avimit for response

By parallel block I mean the block specified by keywords fork join in Verilog.
And by sequential block I mean the block specified by keywords begin end in Verilog.

I think that any behaviour requiring parallelism could be implemented via sequential block with non-blocking assignments in it. And consequently, it is not clear the necessity of parallel blocks in Verilog. It seems they are redundant.
 

avimit

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verilog parallel blocks

I am only talking about RTL, i.e synthesizeable code. And I would still stand by what I said.
As far has behavioral modelling is concerned, I wont say furthur, as it is not my domain.#
Kr,
Avi
 

Arik

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So, you mean that parallel block defined by the fork and join keywords is not synthesizable ? If it is not then it means that parallel block is intended for simulation only.
 

avimit

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Yes, fork-join as far as I know are for simulation modelling only. But I am more into VHDL than verilog, so if somebody reading this can verify my assertion, I would be happy
Kr,
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Arik

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OK, avimit

The parallel block in Verilog is really unsynthesizable and is used for simulation purposes only. Finally I have clarified this question for me. I did some experiments with ModelSim simulator, tried all 4 available combinations of 2 considered Verilog constructs: parallel/sequential blocks and blocking/non-blocking assignments. And here are the results:

1. Sequential block with blocking assignments
The statements in a sequential block are processed in the order they are specified. A statement is executed only after its preceding statement completes execution. If delay or event control is specified, it is relative to the simulation time when the previous statement in the block completed execution.


2. Sequential block with non-blocking assignments
If no regular delays are specified then the right-hand expressions of all non-blocking statements are evaluated then the assignments are performed according to intra-assignment delays. If regular delay controls are specified then the execution order of non-blocking assignments is defined by regular delay controls.


3. Parallel block with blocking assignments
In case of parallel blocks all the statements start to execute at time 0. However the
sequence of statements is still being taken into account. That is the variables used in each succeeding statement take the values assigned to them in preceding statements.

4. Parallel block with non-blocking assignments
In this case all the statements start to execute at time 0 and the right-hand expressions of all statements are evaluated immediately provided that there are no regular delays. It means that the variables used in each succeeding statement does not take the values assigned to them in preceding statements.

So summarizing all these cases one can say that by blocking/non-blocking statements it is controlled whether the values of variables assigned to them in preceding statements are used in succeeding statements or not. And by the Sequential/Parallel blocks it is controlled whether the simulation time is relative to the time when previous statement completed it's execution or to the time when the
block was entered.
 

avimit

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hi,
Well, good to read through your results. But as I said, these are all realted to simulation and not synthesis. And I still stand by what I said earlier, as far as synthesis is concerned.
Kr,
Avi
 

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