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A number of techniques can be used to minimise interconnect capacitance.
1. Space metals futher apart. ie instead of metal 1 & 2 crossing use metal 1 & 3 this will increase the di-electric ( oxide) and lower the capacitance.
2. reduce the amount of squares used to reduce capacitance, this will increase the resistance !
3. Reduce fringing by spacing signals edges signals further apart.
4. aviod sheilding where can dont really need it, it can cause more problems than its worth.
really parasitic capacitances sizes or values in your design are not very important when your load or compensation capasitor is high; that is, when you achieve a safe phase margin for you specific application (low or high accuracy) this means that your nondominant poles(zeros) is high enough according to your gain-bandwidth product.
however, when use small load cap to reach higher speeds, then your parasitic caps must be small enough; thus choosing not very large aspect ratios (W/L) for minimum channel lengths of transistors (otherwise if required) is needed, but your gain of your amplifier may be lower significantly;
however there is a trade-off between them!
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