Deep Nwell noise reduction

[alehan99]

HI
I wonder to know how Deep Nwell could improve the total noise isolation of analog NMOS transistor in digital noisy environment. I know that DNW should isolate the NMOS bulk from bulk noise ( in addition to guard ring) but the Analog and Digital blocks shares the same supplies, means that both analog and digital blocks should see the same supply noise without any filter separation between VDD of digital and VDDA of analog, i. e. VDDA = VDD are the same by value and by noise.

I think that DNW in this case filters the bulk noise but harms the performance cause an additional VDD noise is coupled to NMOS analog transistors through DNW connected to VDD, and this noise is higher than filtered bulk noise.

p.s. analog circuit operates in low frequencies ( up to 1M) and rounded from all sides by digital blocks.
Thanks

 

[lazybear]

hi alehan99,
i'm not sure what kind of noise you're talking about, if you're worrying about coupling noise, layout practice will help, follow scheme 2 & 3, they always work.

 

[alehan99]

hi alehan99,
i'm not sure what kind of noise you're talking about, if you're worrying about coupling noise, layout practice will help, follow scheme 2 & 3, they always work.
View attachment 163672

Hi Lazybear, thank you for your answer. My point is - the first (left ) one case, when both gnd and VDD are shared for Analog and Gid parts, means analog supply have the same noise as digital supply and see all the spikes 1:1 generated there. In this case, DNW connection should filter the substrate noise but couple the VDD noise to NMOS transistors... the same question about Guart-ring rounding an analog block in digital environment, that connected also to gnd /vdd.

 

[lazybear]

hi alehan99,
ok, I get your point. Basic concept of noise isolation is separating quite area from all sources of noise. So, there are physically 2 sources:
1. body noise:
. we will have DNW, or high resistance implant to isolate that thing.
. layout practice: sensitive signals route by M1 is prohibited, or some other layout techniques.
2. metal noise:
. noise suppress through power line like the most left case, that while the 2 right cases are recommend.
. coupling by constantly signals like clocks: preventing by shield or placing from a distant.
....
Actually, good noise isolation is a combination of many stuffs, one stuff alone (like DNW) is not enough.
that's why like i said, good layout practices will help.

 

[alehan99]

Laybear, thank you for your answer.

I agreed with all the claims above, but, sorry, the answer is too general...

I have the case that properly described by case 2 ( middle ) on the plot diagram above .

Given: small analog block (say thermal sensor 30ux30u ), is placed in the center of the digital environment ( surrounded by digital blocks) and shares digital power supplies (very noisy supplies with high transients without any filtering. there are no any other quiet bias or power supply around).
For the external noise filtering ( from digital domain), there are only two things that I have a guard ring and DNW layer(deep n-well)

The only voltage that DNW could be connected is VDD (noisy supply voltage shared with digital and not filtered) .

My suggestion is that DNW filters substrate noise (mostly at low frequencies) but couples VDD noise and this noise is higher than the substrate one.

My claim is that DNW harms the performance , cause VSS and VDD noise is summarized on NMOS transistors. - increased about 2 times.

in addition, DNW requires bigger area.

 

[lazybear]

hi alehan99,
Actually, i haven't met the broke performance issue before when i follow the middle diagram, also, i don't think coupling noise is large enough to transfer from digital through the pad to analog to cause your claim.
by the way, in you given case, people usually uses high resistance implant like BFMOAT(or NT_N, or something depend on process). If possible, you can use this method instead of DNW, so you can clear out your doubt. However, area will be bigger than using DNW.
Moreover, have you check the location of sensor pad? in sensor design, sensor pads is usually surrounded by quite and stable pad.

 

[BigBoss]

AVDD and DVDD are always separated and GND connections are also separated. Therefore digital circuits should not disturb the sensitive analog part.
At least in theory..

 

[alehan99]

hi alehan99,
Actually, i haven't met the broke performance issue before when i follow the middle diagram, also, i don't think coupling noise is large enough to transfer from digital through the pad to analog to cause your claim.
by the way, in you given case, people usually uses high resistance implant like BFMOAT(or NT_N, or something depend on process). If possible, you can use this method instead of DNW, so you can clear out your doubt. However, area will be bigger than using DNW.
Moreover, have you check the location of sensor pad? in sensor design, sensor pads is usually surrounded by quite and stable pad.

Thank you for your reply
1. resistance is a good practice but its performance as i understand similar to guard ring and thus less effective if compare to DNW with quiet VDD connection.
2. sensor pad is a good practice but Thermal sensor in my case defined as IP that shouldn't depend on placement and any distance to pads.

Thank you for you answers, I`ve got the point and now the issue is more clear for me.