predator89
Member level 1
Hello everyone,
I did the paracitic extraction of designed layout. But the simulation results of the extracted view gives 40% variation in for phase margin and settling time. I think there is lot of paracitic capacitance adding through my layout.
This is my first layout and now I want to debug my layout to reduce paracitics. I wanted to know how I can find the nodes in my layout which is adding more paracitics. Also please suggest me methods to reduce the paracitic capacitance.
Any help will be welcome.
Thanks in advance.
Cheers
I did the paracitic extraction of designed layout. But the simulation results of the extracted view gives 40% variation in for phase margin and settling time. I think there is lot of paracitic capacitance adding through my layout.
This is my first layout and now I want to debug my layout to reduce paracitics. I wanted to know how I can find the nodes in my layout which is adding more paracitics. Also please suggest me methods to reduce the paracitic capacitance.
Any help will be welcome.
Thanks in advance.
Cheers