PADC design problems ,could you pls help me?

[pengying]

hello guys

I am now designing a pipelined ADC.But i am very confused about some points.
Assume an ADC of 10bit,and it adopts 1.5b/stage and SHA-including architecture.
So how accurate the MDAC of first stage should be?10 bit? or 9 bit? why ? could you please give me some refrence papers?
Let us consider MDAC of first stage, what the mismatch requirement of capicitors? why? could you please give me some refrence papers?
How large the DC gain of OPAMP shoul be for the first stage? why? could you please give me some refrence papers?
How large the GBW of OPAMP should be for the first stage? why? could you please give me some refrence papers?

 

[sethtalk]

all your question can be find in the follow book
Data Converters, FRANCO MALOBERTI , Springer
Springer - International Publisher Science, Technology, Medicine