PAD parasitice capacitance in IBM 130nm

[soa]

Hello all,

Since I can't extract the parasitic capacitance of the pads, I want to know what is the value of PAD parasitic capacitance in IBM 130nm?

thanks

 

[erikl]

Strongly depends on the capacitance of associated output drivers and the ESD protection. I'd recommend to calculate with 10pF (w.c.), 5pF (typ.), and 1pF (best case).

 

[soa]

Strongly depends on the capacitance of associated output drivers and the ESD protection. I'd recommend to calculate with 10pF (w.c.), 5pF (typ.), and 1pF (best case).

thanks for reply, I am using pad power with standard dimension as input signal.

since I want to connect the ASIC to a device with unknown output capacitance, a more precise range value is important for me

 

[erikl]

I am using pad power with standard dimension as input signal.

A power pad always includes a strong ESD protection, so you should calculate with the a.m. figures. 130nm pad libs state a max. pad input capacitance of 10pF - even for pure input pads (with ESD protection).

If you can get rid of the ESD protection you could get down to about 1pF. The (naked) pad alone contributes 0.6 .. 1pF .