If you name that net as a global (e.g. mustPokeNet!
rather than mustPokeNet) you can attach "stuff" to
it from any level of hierarchy. At least, in analog schematic
based simulations; I believe you ought to be able to make
that net a global in HDL circuit descriptions as well, but
know nothing about RTL design approaches.
Now this would be bad news if you use more than one
of these blocks, of course.
A design which requires external access to non-accessible
nodes, is bad news. You'll pay for it in production, if it
ever gets that far (more likely, stuck in test / debug hell).
But perhaps this is only for purposes of analysis, not
purposes of design closure.