output files of synthesis in ASIC design flow

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bala_EE

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What is are .sdc .ddc and .sdf files and what is the difference between them?

I understand that .sdf file is the one that is used for the place & route step and it has the timing information.

Can anybody explain what exactly does the .sdf file contain?
 

I beleive the second sentence you wanted to write .sdc, means synopsys design constraints, has usually used for synthesis & P&R & STA.
.sdf: is used to back annotated the netlist simulation with timing information, in three corner best, worst & typical.
.ddc : I'm never used this one.
 

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