Output ADC evaluation

[membership]

Dear all hi;
I implemented sigma delta ADC on FPGA I have some questions about evaluating the output ADC..

when I captured the output of my 8-bit ADC it does not digitized from 0-255 and it only digitized from e.g [30, 237] at fin=20 hz; and [10, 196] at fin=10khz ...in output frequency range.

I want to know does it seems like a problem in designing ADC? since my analog input pass through an off-chip RC integrator before entering to FPGA and its gain will change at the entrance of FPGA.

and the second question is at least how much ENOB is accepted for 8-bit ADC for common applications not precise one?
Thank you

 

[barry]

Most importantly, what is your sample rate? Unless your sample rate is a LOT faster than your input clock, you will very likely miss the peaks and valleys of your input signal. Further, have you verified that your input range matches your ADC range? If you are trying to characterize the resolution, why don't you use a DC input? or a much slower input frequency?

As far as your second question goes, let me answer it with a question: How fast do I need to drive from New York to Boston?

 

[rca]

the timing at the fpga interface need to be handle carrefully with your external analog component.
for example, work on opposite edge, to add the half-period of marge.

 

[membership]

Dear barry thanks for ur reply...

Most importantly, what is your sample rate? Unless your sample rate is a LOT faster than your input clock, you will very likely miss the peaks and valleys of your input signal.

my input clock is 50MHz and output sample rate is 195ksps. so there is no problem in this case.


Further, have you verified that your input range matches your ADC range?

yes; my ADC range and input range both are [0, 3.3V]

If you are trying to characterize the resolution, why don't you use a DC input? or a much slower input frequency?

You are right; ُSince I want to evaluate the operation of my ADC I want to know that if I use a DC input = 0V, 1.65V, 3.3V and capture the output from ADC then should I expect to see the codes around 0, 128, 255 respectively? I want to add this that the amplitude of my ADC input and output are not equal according to the gain in my modulator that is less than 1, doesnt this cause to limit the codes?


As far as your second question goes, let me answer it with a question: How fast do I need to drive from New York to Boston?

I understand what you mean, but I want to know for example an ENOB = 5.78 good enough for some applications or not?

your points of view about each conversation is very valuable for me.
Thank you

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the timing at the fpga interface need to be handle carrefully with your external analog component.
for example, work on opposite edge, to add the half-period of marge.

Thank you rca;
do you mean the time constant of sigma delta modulator integrator?
can you tell me how can I handle this timing at the FPGA?
Thank you

 

[barry]

I still don't think you understand your own question about ENOB. The application dictates what is required, not the other way around. 5.78 is "good enough" for some applications, not good enough for others.

 

[rca]

I means timing interface independant of what is in the FPGA, but just to take care of the timing from going out the FPGA and go to external component.