Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SDC constraints for MUXed clock input + clock divider + MUXed clock output

shlooky

Member level 2
Member level 2
Joined
Nov 15, 2011
Messages
43
Helped
3
Reputation
6
Reaction score
9
Trophy points
1,288
Location
Slovakia
Activity points
1,617
Hi there,

I am trying to write SDC contraints for given design...
Input clocks are defined by "create_clock" commands (not shown in the picture).
MUXes are covered by "set_clock_groups" commands.
Freq_div outputs should be covered by "create_generated_clock" commands.

I am not 100% sure about the pin definitions, could you guys please check it?

Am I missing something?
Any advice maybe?

Thanks in advance...

drawing.png
 
Last edited:

shlooky

Member level 2
Member level 2
Joined
Nov 15, 2011
Messages
43
Helped
3
Reputation
6
Reaction score
9
Trophy points
1,288
Location
Slovakia
Activity points
1,617
Hi,

Thanks for the reply. The tool is fine with the definitions
I am more concerned about the timing results based on SDC / correct constraining of muxed input and output.

See, I am not familiar with muxed clock designs at all and the picture/SDC commands are just what I've gathered online, but there are conflicting (and confusing) answers so I wanted more experienced designer to look at it and maybe clear things up.

Shlooky
 
Last edited:

rca

Advanced Member level 5
Advanced Member level 5
Joined
May 20, 2010
Messages
1,527
Helped
355
Reputation
710
Reaction score
335
Trophy points
1,363
Location
Marin
Activity points
8,771
why not just defining:
1. a clock network from mux_in.Z and stop to mux.out input pins to equilibrate the flop inside the divider.
2. a clock network from mux_out.Z, to equilibrate the remaining design.

OR

transform the FREQ_DIV to generate a clock enable signal with will acts on the clock gating cell, so no need of the mux_out.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top