Ouput Conjugate Matching not done right?

[Grecs]

I have the schematic of the photo working at 2.4 GHz. I clearly get around 3V peak to peak before C0 but at my port2 (50ohm) I get like 160mV.

I have done matching and have checked it. Doing an SP simulation Z22 is approximately 50ohm with zero imaginary and Zm2 the same. Also S22 is around zero (10^(-3)) so I guess the matching is ok. Whats wrong with the power loss? I really cant understand and is buffling me some weeks....

 

[BigBoss]

You did DC short circuit the drain of M4 with M1 M0 switch circuit.( M0 and M1 act as a switch, not amplifier)

 

[Grecs]

You did DC short circuit the drain of M4 with M1 M0 switch circuit.( M0 and M1 act as a switch, not amplifier)

hmm? Vsg=0.9V > |Vt|=0.5V
so Vsd>Vsg-|Vt|
Vs-Vd>0.9-0.5
1.8-Vd>0.4
so Vd<1,4V

To work on saturation. Isnt that right for the PMOS?

Also if I transient analyse the short circuit of drain of m4 with Source of m0-m1 I get 155mV peak to peak and at drain of M0 M1 I have 2.5V peak to peak.

 

[BigBoss]

hmm? Vsg=0.9V > |Vt|=0.5V
so Vsd>Vsg-|Vt|
Vs-Vd>0.9-0.5
1.8-Vd>0.4
so Vd<1,4V

To work on saturation. Isnt that right for the PMOS?

Also if I transient analyse the short circuit of drain of m4 with Source of m0-m1 I get 155mV peak to peak and at drain of M0 M1 I have 2.5V peak to peak.

Why don't you try to insert a ideal capacitor between 2 stages ?? I'm saying M4 does not amplify the signal properly because VDS voltage is very low because of short circuit (more or less)

 

[Grecs]

I tried with capacitor before the node and the amplification is far worse and same problem occurs. Then I tried with inductor and results are the same. Loss of power after the L network. I read 2 papers with this topology and both use a short circuit between the D of nmos and S of PMOS. I think the problem is that I dont measure Zout properly.

 

[BigBoss]

I tried with capacitor before the node and the amplification is far worse and same problem occurs. Then I tried with inductor and results are the same. Loss of power after the L network. I read 2 papers with this topology and both use a short circuit between the D of nmos and S of PMOS. I think the problem is that I dont measure Zout properly.

Is the mid point connection of the coil connected to GND, is it midpoint ot substrate ??
If it's a midpoint, you made short circuit the supply.If it is not, check the DC operating point and post them here..