Oscillations on silicon...

[ashish_chauhan]

Hi ,

I did a micro-power bandgap design recently...
The design gives pretty good results on pre and post layout simulations...

BUT ... on silicon its showing 1volt peak to peak oscillations...

any sugesstions to debug the silicon..

thanks.

 

[renwl]

can you show your circuit?

if you used opamp, maybe the opamp is the source.

 

[ashish_chauhan]

Its something like this ...

very basic architecture...

 

[apm70]

Hi,

I have the same circuit and the same problem... bad oscillation, but only in silicon.
If you have found a solution by now, please tell me.

Thanks!

 

[yxo]

If the amplifier is OTA might be problem without compensate capacitor at its' output. At first, I'd recomend to set small maxstep in the transient options and check for oscillation.

 

[apm70]

It is a 2 stage ota with miller capacitor and a capacitor from its output (the gates of the pmos mirror) to vdd.
I just cant reproduce the oscillation in simulation (conservative transient with small maxstep, vdd ramped up quickly). However, in silicon all the chips have unstable output due to some bad oscillation...

 

[yxo]

Another thing, during start-up the output range of the amplifier can exceed the input range of the MOSFETs. So, loop gain can increase and the one won´t be stable anymore. I attached some refeerence. You can try to start your chip softly,by a slower increase of the power supply voltage.

 

[apm70]

Thanks, I will try that next time I test the chip.
The bandgap is used in a micropower application. (No need for great precision)Could the stability issue have something to do with the very low branch current (140nA)? ashish_chauhan also had a micropower application and he had the same problem.

 

[elbadry]

Do you simulate with the actual loads?

You can use Spectre to do a stability analysis to find the bandgap loop gain, phase margin and gain margin. A small phase/gain margin in simulation might cause oscillations in silicon i guess..

 

[sutapanaki]

yxo,

What is the title of the book that you posted?

 

[yxo]

OPERATIONAL AMPLIFIER
SPEED AND
ACCURACY IMPROVEMENT
Analog Circuit Design
with Structural Methodology
by
Vadim V. Ivanov
Texas Instruments, Inc.
and
Igor M. Filanovsky

 

[apm70]

I did the cadence stability analysis (stb), and found that the phase margin is actually quite low (14 degrees, even less for some corner/temperature). I can raise it significantly (>60) by increasing the branch current, and some other minor modifications. I think that should solve the problem i see on silicon.