quaternion said:If the oscillation appears after appling a monopulse (like that in the topic I made), I advice you to find the loop gain and phase at different current loads.(sweep the load current and monitor the loop gain and phase)
elmolla said:What do you mean by applying a monopulse? These oscillations appear without any perturbation to the circuit :|
I've done a load sweep to check the phase margin across loads and it was inconclusive; it seems always stable
ashish_chauhan said:elmolla said:What do you mean by applying a monopulse? These oscillations appear without any perturbation to the circuit :|
I've done a load sweep to check the phase margin across loads and it was inconclusive; it seems always stable
what does that mean... the phase margins are always the same or its just that u have safe margins...
coz in former case you can doubt the sim results...
LvW said:Hi elmolla,
by the way - did you do already something against the oscillations (independent on the weird loop gain results) ?
Up to now we didn´t speak about the output compensation capacitor and its real part.
Can you give some information on this ?
ashish_chauhan said:probably he is refering to the "esr"
can you tell what exactly did you do as a modification?
quaternion said:If you are designing on chip cap ldo then you shouldn't use esr.
It is used for off chip cap ldo.
For off chip cap ldo : large esr gives larger spikes while smaller esr degrades PM.
It seems that you are designing on chip cap ldo ?
about the amplifier : did you try class AB second stage?
ashish_chauhan said:quaternion said:If you are designing on chip cap ldo then you shouldn't use esr.
It is used for off chip cap ldo.
For off chip cap ldo : large esr gives larger spikes while smaller esr degrades PM.
It seems that you are designing on chip cap ldo ?
about the amplifier : did you try class AB second stage?
Are'nt you using an off chip cap?
and as for esr in offchip case it won't neccesarily degrade the pm... depends on how you are trying to compesate the loop.
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