LvW said:What is the orientation of the PMOS ?
Common source or common drain arrangement ? The question is important because both configurations have different stability properties.
Added after 31 minutes:
Forget my last question.
As you use a PMOS device it will work in common source operation with Vdrain=Vin and Vout=Vsource.
Only to be sure: The reference voltage is connected to the inverting and the signal from the resistive divider to the noninv. opamp terminal, right ?
LvW said:There is something which came into my mind just now:
When we require to ground the input signal during loop gain (i.e. stability) analysis, you should take care of a correct bias point of course.
To be specific: The drain should be connected to the unregulated voltage also during loop gain simulation (otherwise there would be no VDS); and the input signal which must be zero during this simulation is just the CHANGE of this voltage.
With other words: ΔVin=0 means Vin=constant.
I suppose, you have taken care of this, don´t you ?
safwatonline said:what are the settings of ur transient simulation testbench
LvW said:Quote elmolla: But I don't know why you want to set the drain to the unregulated voltage? The PMOS is in a common source configuration where the source should be connected to the unregulated voltage and the drain should be the only which supplies the regulated voltage?
You are right, sorry - I have mixed source and drain.
Added after 19 minutes:
Hi elmolla:
Do you mind showing us a diagram of the BODE diagram for loop gain (magnitude
and phase) ?
safwatonline said:ok, what i mean is:
1- usually when Transient shows oscillation then you are unstable (i.e. trust the tran sim.)
2- if AC shows stable operation then most probably there is difference between transient simulation and AC (i.e. AC is small signal analysis around some DC operating point, so i guess the AC is at a stable operating point while the tran passed through some unstable operating point)
3- so as a suggestion maybe you divide the start-up into some steps (i.e. if u are ramping the supply then do smaller ramps, if u r stepping the load current also do smaller steps, also try to reverse the step direction i.e. from higher current to lower ...etc) this is done to try to get the boundary of oscillation, which means when the circuit exactly starts to oscillate (then once u know that point u should do AC analysis on this point)
tab3an elkalam dah kolo kalam fare3' matsada2sh 2y 7aga menoo, w ba3deen 2oom zaker w seebak men eldesign delwa2ty
ashish_chauhan said:Hi Emolla
just check the saturation margins of the devices in ur design...
if its low then a transient pulse/step can throw ur device out of saturation and it might never recover back reulting into oscillations.
So take a operating point calulation from ur transinent sims.
ashish_chauhan said:By saturation margins I mean ur devices shud be having enough vds as compared to vdsat...
vds shud not be marginally greater than vdsat...
Added after 2 minutes:
"I've done another simulation of load switching between a stable and unstable point. The oscillations aren't altered! It just keeps in a state of sustained oscillations of peak to peak value about 8% around the stable operating point, even after passing through he stable operating loading:!: "
Then probably I am pointing in right direction.
elbadry said:Did you check the gain margin?
Phase Margin is not enough for ensuring stable operation in systems with multiple
zeroes and poles. You must have a high enough phase and gain margins
LvW said:That´s correct. Good idea. One should have known earlier.
elmolla said:I feel a misconception here LvW; How would I use a commercial opamp in an analog IC design? This isn't a discrete circuits, it is integrated.
I know showing the schematic would help a lot but I can't show the schematic as I've pointed before.
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