eng.obd_md
Newbie level 4
Hi,
I am designing an intensive control algorithm in FPGA. The problem my design have a very good results more than good enough. How can I tradeoff the throughput to area if my design is a big statemachine (170 state minimum)?. Now if it was a datapath like a DCT,FFT etc one could suggest folding the algorithm. but what can I do with a state machine?
The tool I am using is Quartus II of altera. However, my question is more on the design level of a state machine. What steps do you take to reduce the resource usage when the algorithm is not mathematically intensive but control intensive.
Very best regards
I am designing an intensive control algorithm in FPGA. The problem my design have a very good results more than good enough. How can I tradeoff the throughput to area if my design is a big statemachine (170 state minimum)?. Now if it was a datapath like a DCT,FFT etc one could suggest folding the algorithm. but what can I do with a state machine?
The tool I am using is Quartus II of altera. However, my question is more on the design level of a state machine. What steps do you take to reduce the resource usage when the algorithm is not mathematically intensive but control intensive.
Very best regards
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