Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
To my opinion, compared with an analog PLL, a DPLL in general has very high jitter. Unless you don't add DDS clock generators (they are actually hybrid analog/digital systems) to digital PLL category.
The jitter could be lower than the analog phase noise contributions of the PLL components. That is also demonstrated by TI!
The key is the digital VCO control and the digital phase detector. The VCO control is not easy to make monotonic and switching spurious noise free and the conversion from time differences to digital data is also difficult.
The question is: does the overall effort of a pure digital result in a more economic chip realization. Both form NRE and silicon area.
It could be that we have different defintions of a digital PLL. In my understanding, a digital PLL works in a discrete time scale, with an output clocked at discrete times. This may look fine in this discrete world, but not when e. g. sampling an analog signal that is unrelated to this time domain. Can you give a reference to one of the said TI papers.
Sorry I have read many papers from TI and seen conference presentations over years. Have many magazines here but did not select one. Do it tomorrow.
The "All-Digital-PLL" is still time-discrete! What change in the concept is that the path phase-difference -> vco-frequency gets value-discrete. So first the phase difference should be converted into a digital value. The integrating property allows to exchange value resolution and time resolution. Then PI-controller is made digital and the vco is finally digital controlled. In the classical "digital PLL" (in Roland Best term) the phase is continuous.
I would like to consider a simple test case. I have a high quality 100 MHz reference clock and want to generate a 54.24 MHz clock with minimum jitter for a digital receiver. I know, I can achieve this with an analog PLL or a DDS clock synthesizer (a mixed signal hybrid, that uses analog interpolation and filtering, I wouldn't regard it a digital PLL). I assume, that a digital PLL can't help in this respect. An all digital solution would set receiver sample rate to either 50 or 100 MHz, for several reasons (ADC nonlinearities, intended output data rate, whatever) this may not be suitable for my receiver.
The jitter could be lower than the analog phase noise contributions of the PLL components. That is also demonstrated by TI!
The key is the digital VCO control and the digital phase detector. The VCO control is not easy to make monotonic and switching spurious noise free and the conversion from time differences to digital data is also difficult.
The question is: does the overall effort of a pure digital result in a more economic chip realization. Both form NRE and silicon area.
For 45, 65 and 90nm technology, the voltage headroom is decreased. and it's more and more difficult to design ADPLL with digital core device. Beside voltage headroom, the gate-leakage is also a big problem for loop filter design. Although thick-oxide device can be used to solve the gate-leakage, but area will be suffered.
from my point of view, in terms of digital core clock generator, all digital PLL is the future.
Hi Guys! I am new to PLL design and must choose which PLL architecture to make. I have not much experience. Can u say which PLL: analog of fully digital to prefer. The Target is to make PLL for frequency synthesis in DSP microprocessor for SOI 0.35um technology. Reference frequency can vary from 10 to 20 MHz. Multipliation factor 1-15. P.S. Sorry if my English bad. It is not my primary lang
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
