Open Verification Libiary Free Download

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davyzhu

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davidyu jeda

Hi all,

I am a Verilog user and I want to find some tools do assertion(like C's assert()).

I found Open Verification Libiary(OVL) has been updated. And it is free for download( https://www.accellera.org/activities/ovl/ ).

I hope to use it in the near future.

Anyone has used it yet? Please give some comment. Thanks!

Best regards,
Davy
 

hi there

does anyone know if these guys have dropped support for VHDL OVL version? It's been more than 2 years since the last refinements on the VHDL version of the OVL.

TIA
the_penetrator©
 

synopsys VCS can support OVL, SVA, cadence IUS support PSL, JEDA support SystemC assertion. only free doc, no free soft can be found.
 

Because of the nature of VHDL, it's not so easy to use those library compared to verilog version. It's no surprise that people don't like to use it.
 

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